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MIMXRT8024DVL4A Datasheet(PDF) 41 Page - NXP Semiconductors |
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MIMXRT8024DVL4A Datasheet(HTML) 41 Page - NXP Semiconductors |
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41 / 103 page  Table 30. JTAG timing (continued) ID Parameter1,2 All Frequencies Unit Min Max SJ11 JTAG_TCK low to JTAG_TDO high impedance — 44 ns SJ12 JTAG_TRST_B assert time 100 — ns SJ13 JTAG_TRST_B set-up time to JTAG_TCK low 40 — ns 1. TDC = target frequency of SJC 2. VM = mid-point voltage 4.4.4 Debug trace timing specifications Table 31. Debug trace operating behaviors Symbol Description Min Max Unit T1 ARM_TRACE_CLK frequency of operation — 70 MHz T2 ARM_TRACE_CLK period 1/T1 — MHz T3 Low pulse width 6 — ns T4 High pulse width 6 — ns T5 Clock and data rise time — 1 ns T6 Clock and data fall time — 1 ns T7 Data setup 2 — ns T8 Data hold 0.7 — ns ARM_TRACE_CLK T5 T4 T6 T2 T3 Figure 13. ARM_TRACE_CLK specifications NXP Semiconductors Electrical Characteristics i.MX RT1060X Crossover Processors for Extended Products , Rev. 1, 06/2022 Data Sheet: Technical Data 41 / 103 |
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