MIMXRT8024DVL4A datasheet(54/103 Pages) NXP

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Table 49. LCD timing parameters (continued)

LCD pixel clock low to data valid (rising edge capture)

td(CLKL-DV)

-1

LCD pixel clock high to control signal valid (falling edge capture)

td(CLKH-CTRLV)

-1

LCD pixel clock low to control signal valid (rising edge capture)

td(CLKL-CTRLV)

-1

4.7 Audio

This section provide information about SAI/I2S and SPDIF.

4.7.1 SAI/I2S switching specifications

This section provides the AC timings for the SAI in master (clocks driven) and slave (clocks input) modes. All timings are given for

non-inverted serial clock polarity (SAI_TCR[TSCKP] = 0, SAI_RCR[RSCKP] = 0) and non-inverted frame sync (SAI_TCR[TFSI]

= 0, SAI_RCR[RFSI] = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timings remain valid by

inverting the clock signal (SAI_BCLK) and/or the frame sync (SAI_FS) shown in the figures below.

Table 50. Master mode SAI timing

Num

Characteristic

Min

Max

Unit

SAI_MCLK cycle time

—

SAI_MCLK pulse width high/low

40%

60%

MCLK period

SAI_BCLK cycle time

—

SAI_BCLK pulse width high/low

40%

60%

BCLK period

SAI_BCLK to SAI_FS output valid

—

SAI_BCLK to SAI_FS output invalid

—

SAI_BCLK to SAI_TXD valid

—

SAI_BCLK to SAI_TXD invalid

—

SAI_RXD/SAI_FS input setup before SAI_BCLK

—

S10

SAI_RXD/SAI_FS input hold after SAI_BCLK

—

NXP Semiconductors

Electrical Characteristics

i.MX RT1060X Crossover Processors for Extended Products , Rev. 1, 06/2022

Data Sheet: Technical Data

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