MIMXRT8024DVL4A datasheet(44/103 Pages) NXP

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4.5.1.2 SEMC input timing

There are ASYNC and SYNC mode for SEMC input timing.

4.5.1.2.1 SEMC input timing in ASYNC mode

Table 34 shows SEMC output timing in ASYNC mode.

Table 34. SEMC output timing in ASYNC mode

Symbol

Parameter

Min.

Max.

Unit

Comment

TIS

Data input setup

8.67

—

For NAND/NOR/PSRAM/DBI,

these timing parameters apply

to RE# and Read Data.

TIH

Data input hold

—

Figure 17 shows the input timing in ASYNC mode.

DATA

OE#

DATA

TIS

TIH

TIS TIH

NAND non-EDO mode and NOR/PSRAM/8080 timing

NAND EDO mode timing

Figure 17. SEMC input timing in ASYNC mode

4.5.1.2.2 SEMC input timing in SYNC mode

Table 35 and Table 36 show SEMC input timing in SYNC mode.

Table 35. SEMC input timing in SYNC mode (SEMC_MCR.DQSMD = 0x0)

Symbol

Parameter

Min.

Max.

Unit

Comment

TIS

Data input setup

8.67

—

TIH

Data input hold

—

NXP Semiconductors

Electrical Characteristics

i.MX RT1060X Crossover Processors for Extended Products , Rev. 1, 06/2022

Data Sheet: Technical Data

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