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MIMXRT8024DVL4A Datasheet(PDF) 87 Page - NXP Semiconductors |
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MIMXRT8024DVL4A Datasheet(HTML) 87 Page - NXP Semiconductors |
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87 / 103 page  Table 83. 13 x 13 mm functional contact assignments Ball Name 12 x 12 Ball Power Group Ball Type Default Setting Default setting on Reset Default Mode Default Function Input/ Output Value Input/ Output Value CCM_CLK1_N R14 — — — CCM_CLK1_N — — — — CCM_CLK1_P P14 — — — CCM_CLK1_P — — — — GPIO_AD_B0_00 M14 NVCC_GPIO Digital GPIO ALT5 GPIO1.IO[0] Input Keeper Input Keeper GPIO_AD_B0_01 H11 NVCC_GPIO Digital GPIO ALT5 GPIO1.IO[1] Input Keeper Input Keeper GPIO_AD_B0_02 P15 NVCC_GPIO Digital GPIO ALT5 GPIO1.IO[2] Input Keeper Input Keeper GPIO_AD_B0_03 J13 NVCC_GPIO Digital GPIO ALT5 GPIO1.IO[3] Input Keeper Input Keeper GPIO_AD_B0_04 G13 NVCC_GPIO Digital GPIO ALT0 SRC.BOOT.MOD E[0] Input 100 K PD Input 100 K PD GPIO_AD_B0_05 H14 NVCC_GPIO Digital GPIO ALT0 SRC.BOOT.MOD E[1] Input 100 K PD Input 100 K PD GPIO_AD_B0_06 G15 NVCC_GPIO Digital GPIO ALT0 JTAG.MUX.TMS Input 47 K PU Input 47 K PU GPIO_AD_B0_07 G14 NVCC_GPIO Digital GPIO ALT0 JTAG.MUX.TCK Input 47 K PU Input 100 K PD GPIO_AD_B0_08 H13 NVCC_GPIO Digital GPIO ALT0 JTAG.MUX.MOD Input 100 K PU Input 100 K PD GPIO_AD_B0_09 H15 NVCC_GPIO Digital GPIO ALT0 JTAG.MUX.TDI Input 47 K PU Input 47 K PU GPIO_AD_B0_10 H12 NVCC_GPIO Digital GPIO ALT0 JTAG.MUX.TDO Input Keeper Input Keeper GPIO_AD_B0_11 G11 NVCC_GPIO Digital GPIO ALT0 JTAG.MUX.TRS TB Input 47 K PU Input 47 K PU GPIO_AD_B0_12 L14 NVCC_GPIO Digital GPIO ALT5 GPIO1.IO[12] Input Keeper Input Keeper GPIO_AD_B0_13 M15 NVCC_GPIO Digital GPIO ALT5 GPIO1.IO[13] Input Keeper Input Keeper Table continues on the next page... NXP Semiconductors Package information and contact assignments i.MX RT1060X Crossover Processors for Extended Products , Rev. 1, 06/2022 Data Sheet: Technical Data 87 / 103 |
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