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MIMXRT8024DVL4A Datasheet(PDF) 79 Page - NXP Semiconductors

Part # MIMXRT8024DVL4A
Description  i.MX RT1060X Crossover Processors for Extended Products
PDF  103 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

MIMXRT8024DVL4A Datasheet(HTML) 79 Page - NXP Semiconductors

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Table 71. Fuses and associated pins used for boot (continued)
Pad
Default setting on reset
eFuse name
Details
GPIO_B0_12
100 K pull-down
BT_CFG[8]
GPIO_B0_13
100 K pull-down
BT_CFG[9]
GPIO_B0_14
100 K pull-down
BT_CFG[10]
GPIO_B0_15
100 K pull-down
BT_CFG[11]
5.2 Boot device interface allocation
The following tables list the interfaces that can be used by the boot process in accordance with the specific boot mode
configuration. The tables also describe the interface’s specific modes and IOMUXC allocation, which are configured during boot
when appropriate.
Table 72. Boot through NAND
PAD Name
IO Function
ALT
Comments
GPIO_EMC_00
semc.DATA[0]
ALT 0
—
GPIO_EMC_01
semc.DATA[1]
ALT 0
—
GPIO_EMC_02
semc.DATA[2]
ALT 0
—
GPIO_EMC_03
semc.DATA[3]
ALT 0
—
GPIO_EMC_04
semc.DATA[4]
ALT 0
—
GPIO_EMC_05
semc.DATA[5]
ALT 0
—
GPIO_EMC_06
semc.DATA[6]
ALT 0
—
GPIO_EMC_07
semc.DATA[7]
ALT 0
—
GPIO_EMC_30
semc.DATA[8]
ALT 0
—
GPIO_EMC_31
semc.DATA[9]
ALT 0
—
GPIO_EMC_32
semc.DATA[10]
ALT 0
—
GPIO_EMC_33
semc.DATA[11]
ALT 0
—
GPIO_EMC_34
semc.DATA[12]
ALT 0
—
GPIO_EMC_35
semc.DATA[13]
ALT 0
—
GPIO_EMC_36
semc.DATA[14]
ALT 0
—
GPIO_EMC_37
semc.DATA[15]
ALT 0
—
Table continues on the next page...
NXP Semiconductors
Boot mode configuration
i.MX RT1060X Crossover Processors for Extended Products , Rev. 1, 06/2022
Data Sheet: Technical Data
79 / 103



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