MIMXRT8024DVL4A datasheet(38/103 Pages) NXP

38 / 103 page

Table 27. GPIO output buffer average impedance (NVCC_XXXX 3.3 V)

Parameter

Symbol

Drive Strength (DSE)

Typ Value

Unit

Output

Driver Impedance

Rdrv

001

010

011

100

101

110

111

157

4.4 System modules

This section contains the timing and electrical parameters for the modules in the i.MX i.MX RT1060X processor.

4.4.1 Reset timings parameters

Figure 7 shows the reset timing and Table 28 lists the timing parameters.

POR_B

CC1

(Input)

Figure 7. Reset timing diagram

Table 28. Reset timing parameters

Parameter

Min Max

Unit

CC1

Duration of POR_B to be qualified as valid.

—

RTC_XTALI cycle

4.4.2 WDOG reset timing parameters

Figure 8 shows the WDOG reset timing and Table 29 lists the timing parameters.

WDOGn_B

CC3

(Output)

Figure 8. WDOGn_B timing diagram

Table 29. WDOGn_B timing parameters

Parameter

Min

Max

Unit

CC3

Duration of WDOGn_B Assertion

—

RTC_XTALI cycle

NXP Semiconductors

Electrical Characteristics

i.MX RT1060X Crossover Processors for Extended Products , Rev. 1, 06/2022

Data Sheet: Technical Data

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