MIMXRT8024DVL4A datasheet(56/103 Pages) NXP

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Figure 32. SAI timing—Slave mode

4.7.2 SPDIF timing parameters

The Sony/Philips Digital Interconnect Format (SPDIF) data is sent using the bi-phase marking code. When encoding, the SPDIF

data signal is modulated by a clock that is twice the bit rate of the data signal.

Table 52, Figure 33, and Figure 34 show SPDIF timing parameters for the Sony/Philips Digital Interconnect Format (SPDIF),

including the timing of the modulating Rx clock (SPDIF_SR_CLK) for SPDIF in Rx mode and the timing of the modulating Tx clock

(SPDIF_ST_CLK) for SPDIF in Tx mode.

Table 52. SPDIF timing parameters

Characteristics

Symbol

Timing Parameter Range

Unit

Min

Max

SPDIF_IN Skew: asynchronous inputs, no specs apply

—

0.7

SPDIF_OUT output (Load = 50pf)

• Skew

• Transition rising

• Transition falling

—

1.5

24.2

31.3

SPDIF_OUT1 output (Load = 30pf)

• Skew

• Transition rising

• Transition falling

—

1.5

13.6

18.0

Modulating Rx clock (SPDIF_SR_CLK) period

srckp

40.0

—

SPDIF_SR_CLK high period

srckph

16.0

—

SPDIF_SR_CLK low period

srckpl

16.0

—

Table continues on the next page...

NXP Semiconductors

Electrical Characteristics

i.MX RT1060X Crossover Processors for Extended Products , Rev. 1, 06/2022

Data Sheet: Technical Data

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