MIMXRT8024DVL4A datasheet(48/103 Pages) NXP

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4.5.2.1.3 DDR mode with FlexSPIn_MCR0[RXCLKSRC] = 0x0, 0x1

Table 41. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x0

Symbol

Parameter

Min

Max

Unit

Frequency of operation

—

MHz

TIS

Setup time for incoming data

8.67

—

TIH

Hold time for incoming data

—

Table 42. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x1

Symbol

Parameter

Min

Max

Unit

Frequency of operation

—

MHz

TIS

Setup time for incoming data

—

TIH

Hold time for incoming data

—

TIS

TIH

TIS

TIH

SCLK

SIO[0:7]

Internal Sample Clock

Figure 22. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x0, 0x1

4.5.2.1.4 DDR mode with FlexSPIn_MCR0[RXCLKSRC] = 0x3

There are two cases when the memory provides both read data and the read strobe in DDR mode:

• B1—Memory generates both read data and read strobe on SCK edge

• B2—Memory generates read data on SCK edge and generates read strobe on SCK2 edge

RT1060X supports two FlexSPI controllers. When FlexSPI2 is accessed through GPIO_SPI_B0/1_XX, the clock

supports up to 133 MHz (both for DDR and SDR mode).

NOTE

Table 43. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (case B1)

Symbol

Parameter

Min

Max

Unit

Frequency of operation

—

166

MHz

TSCKD

Time from SCK to data valid

—

TSCKDQS

Time from SCK to DQS

—

TSCKD - TSCKDQS

Time delta between TSCKD and TSCKDQS

-1

NXP Semiconductors

Electrical Characteristics

i.MX RT1060X Crossover Processors for Extended Products , Rev. 1, 06/2022

Data Sheet: Technical Data

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