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MIMXRT8024DVL4A Datasheet(PDF) 68 Page - NXP Semiconductors |
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MIMXRT8024DVL4A Datasheet(HTML) 68 Page - NXP Semiconductors |
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68 / 103 page  2 10 6 7 MSB IN BIT 6 . . . 1 SLAVE MSB SLAVE LSB OUT 11 5 5 3 8 4 11 SEE NOTE 9 see note (INPUT) (CPOL=0) SCK SCK (CPOL=1) PCS (INPUT) (INPUT) SOUT (INPUT) SIN (OUTPUT) LSB IN BIT 6 . . . 1 NOTE: Not defined Figure 41. LPSPI Slave mode timing (CPHA = 0) 2 6 7 MSB IN BIT 6 . . . 1 MSB OUT SLAVE LSB OUT 5 5 10 3 4 SLAVE 8 9 see note (INPUT) (CPOL=0) SCK SCK (CPOL=1) PCS (INPUT) (INPUT) SOUT (INPUT) SIN (OUTPUT) 11 LSB IN BIT 6 . . . 1 NOTE: Not defined Figure 42. LPSPI Slave mode timing (CPHA = 1) 4.9.2 LPI2C module timing parameters This section describes the timing parameters of the LPI2C module. Table 59. LPI2C module timing parameters Symbol Description Min Max Unit Notes fSCL SCL clock frequency Standard mode (Sm) 0 100 kHz 1, 2 Fast mode (Fm) 0 400 Fast mode Plus (Fm+) 0 1000 Table continues on the next page... NXP Semiconductors Electrical Characteristics i.MX RT1060X Crossover Processors for Extended Products , Rev. 1, 06/2022 Data Sheet: Technical Data 68 / 103 |
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