MIMXRT8024DVL4A datasheet(72/103 Pages) NXP

72 / 103 page

Table 62. SDR50/SDR104 interface timing specification (continued)

Parameter

Symbols

Min

Max

Unit

uSDHC Output/Card Inputs SD_CMD, SDx_DATAx in SDR104 (Reference to CLK)

SD5

uSDHC Output Delay

tOD

–1.6

uSDHC Input/Card Outputs SD_CMD, SDx_DATAx in SDR50 (Reference to CLK)

SD6

uSDHC Input Setup Time

tISU

2.5

—

SD7

uSDHC Input Hold Time

tIH

1.5

—

uSDHC Input/Card Outputs SD_CMD, SDx_DATAx in SDR104 (Reference to CLK)1

SD8

Card Output Data Window

tODW

0.5 x tCLK

—

1. Data window in SDR104 mode is variable.

4.9.3.4 HS200 mode timing

Figure 46 depicts the timing of HS200 mode, and Table 63 lists the HS200 timing characteristics.

SCK

8-bit output from uSDHC to eMMC

8-bit input from eMMC to uSDHC

SD8

SD4/SD5

SD2

SD3

SD1

Figure 46. HS200 mode timing

Table 63. HS200 interface timing specification

Parameter

Symbols

Min

Max

Unit

Card Input Clock

SD1

Clock Frequency Period

tCLK

5.0

—

SD2

Clock Low Time

tCL

0.46 x tCLK

0.54 x tCLK

SD3

Clock High Time

tCH

0.46 x tCLK

0.54 x tCLK

uSDHC Output/Card Inputs SD_CMD, SDx_DATAx in HS200 (Reference to CLK)

SD5

uSDHC Output Delay

tOD

–1.6

0.74

Table continues on the next page...

NXP Semiconductors

Electrical Characteristics

i.MX RT1060X Crossover Processors for Extended Products , Rev. 1, 06/2022

Data Sheet: Technical Data

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