MIMXRT8024DVL4A datasheet(47/103 Pages) NXP

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TSCKDQS

SCK

SIO[0:7]

DQS

TSCKD

TSCKDQS

TSCKD

Figure 20. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0X3 (case A1)

Timing shown is based on the memory generating read data and read strobe on the SCK rising edge. The FlexSPI

controller samples read data on the DQS falling edge.

NOTE

Table 40. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (case A2)

Symbol

Parameter

Value

Unit

Min

Max

Frequency of operation

—

166

MHz

TSCKD

Time from SCK to data valid

—

TSCKDQS

Time from SCK to DQS

—

TSCKD - TSCKDQS

Time delta between TSCKD and TSCKDQS

-2

TSCKDQS

TSCKD

SCK

SIO[0:7]

DQS

Internal Sample Clock

TSCKDQS

TSCKD

TSCKDQS

TSCKD

Figure 21. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0X3 (case A2)

Timing shown is based on the memory generating read data on the SCK falling edge and read strobe on the SCK

rising edge. The FlexSPI controller samples read data on a half cycle delayed DQS falling edge.

NOTE

NXP Semiconductors

Electrical Characteristics

i.MX RT1060X Crossover Processors for Extended Products , Rev. 1, 06/2022

Data Sheet: Technical Data

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MIMXRT8024DVL4A Datasheet(PDF) 47 Page - NXP Semiconductors

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