S32K311NHT0MPAST datasheet(138/143 Pages) NXP

138 / 143 page

Rev 2 Draft B, Mar 2021

— "Power management system - S32K358" figure added.

• In section "Supply Monitoring", Symbol "HVD_V15" is added.

• In section "Supply Monitoring", for "LVD_VDD_HV_A", symbol and description updated.

• Added section "SMPS regulator electrical specifications"

• In section "NPN Ballast Transistor Control Specification", fig with title "Ballast circuit" is changed.

• In section "Supply currents" and "operating mode" tables are updated.

• In section "GPIO DC electrical specifications, 3.3V Range (2.97V - 3.63V)", fig with title "Reference Load Diagram" is

changed.

• In section "GPIO DC electrical specifications, 3.3V Range (2.97V - 3.63V)", footnote updated "A positive value is

leakage flowing into...".

• In section "GPIO DC electrical specifications, 5.0V (4.5V - 5.5V)", Symbol "ILKG_50_S_PTE13" with condition "PMC

VRC_CTRL pin" is added.

• In section "GPIO DC electrical specifications, 5.0V (4.5V - 5.5V)", footnote updated "A positive value is leakage flowing

into...".

• In section "GPIO DC electrical specifications, 5.0V (4.5V - 5.5V)", fig with title "Reference Load Diagram" is changed.

• In section "Flash memory specification", added specs for 512KB and 2MB specifications.

• In table "Flash memory AC timing specifications", taistop max updated.

• Updated "Flash Read Wait State Settings"

• In section "Low Power Comparator (LPCMP)", updated IDLSS typ to 17uA.

• In section "Low Power Comparator (LPCMP)", updated INL and DNL.

• In section "Low Power Comparator (LPCMP)", updated paragraph "For devices where the VDD_HV_B domain is

present..."

• In "Low Power Comparator (LPCMP)" added hysterisis plots.

• In section "PLL", symbol "FPLL_out" description updated to add (PLL_PHIn_CLK)

• In section "PLL", "IPLL_V25" deleted.

• In section "PLL", updated jitter specifications.

• In section "FXOSC", updated paragraph "To improve the FXOSC jitter and duty cycle performance...".

• In section "SXOSC", updated description of "ISXOSC" to Oscillator Analog circuit supply current.

• In section "I2C", added paragraph "For supported baud rate ....."

• Added section "I3C".

• In section "FlexCAN characteristics", added paragraph "For supported baud rate ....."

• Added QuadSPI DDR electrical specifications for Octal and Quad.

• Added uSDHC specifications.

• Updated "Thermal characteristics" and "Obtaining package dimensions"

Rev 2 Draft A, Nov 2020

• Updated features to show maximum memory support up to 8 MB.

NXP Semiconductors

Revision history

S32K3xx Data Sheet, Rev. 9.1, 03/2024

Data Sheet: Technical Data

Preliminary Information for S32K388

138 / 143

S32K311NHT0MPAST Datasheet(PDF) 138 Page - NXP Semiconductors

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