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S32K311NHT0MPAST Datasheet(PDF) 82 Page - NXP Semiconductors |
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S32K311NHT0MPAST Datasheet(HTML) 82 Page - NXP Semiconductors |
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82 / 143 page ![]() For devices where the VDD_HV_B domain is present, LPCMP0 channels must only be selected/enabled when VDD_HV_A >= VDD_HV_B. These channels must be disabled when VDD_HV_A goes below VDD_HV_B. 0 3.3 3.0 1.5 2.1 0.6 30 60 Hysteresis (mV) 0 Vin level (V) Junction Temp (°C) VDD_HV_A (V) HYSTCTR setting 0.3 1.2 2.4 2.7 0.9 1.8 3.3 25 90 00 01 10 11 Figure 36. Typical Hysteresis vs Vin level (VDD_HV_A = 3.3 V, High Speed Mode) 0 3.3 3.0 1.5 2.1 0.6 20 40 60 Hysteresis (mV) 0 HYSTCTR setting 0.3 1.2 2.4 2.7 0.9 1.8 3.3 25 00 Vin level (V) Junction Temp (°C) VDD_HV_A (V) 01 10 11 Figure 37. Typical Hysteresis vs Vin level (VDD_HV_A = 3.3 V, Low Speed Mode) NXP Semiconductors Analog modules S32K3xx Data Sheet, Rev. 9.1, 03/2024 Data Sheet: Technical Data Preliminary Information for S32K388 82 / 143 |
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