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S32K311NHT0MPAST Datasheet(PDF) 58 Page - NXP Semiconductors |
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S32K311NHT0MPAST Datasheet(HTML) 58 Page - NXP Semiconductors |
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58 / 143 page ![]() 8. For the maximum allowable RUN current in an application, the junction temperature must be kept below the maximum specification, TJ < 150°C, to avoid self-heating. 9. If the total power dissipation would cause the junction temperature to be exceeded when VDD_HV_A is at 5V, then VDD_HV_A should be limited to operate at 3.3V. 6.8 Operating mode Table 21. STANDBY and low speed RUN configuration options MODULE STANDBY All OFF STANDBY SIRC ON STANDBY FIRC ON BOOT Mode (OptionC1, FIRC @24 MHz) Low Speed RUN (OptionE 1, FIRC @ 3MHz) FIRC Mode (OptionD 1, FIRC @48 MHz) Core M7_0/1 OFF OFF OFF 24 MHz 3 MHz 48 MHz HSE_B OFF OFF OFF 24 MHz 3 MHz 48 MHz FIRC OFF OFF 24 MHz 24 MHz 3 MHz 48 MHz FXOSC OFF OFF OFF OFF OFF OFF SIRC OFF ON OFF ON ON ON PLL OFF OFF OFF OFF OFF OFF Flash OFF OFF OFF ON ON ON eDMA OFF OFF OFF ON ON ON FlexCAN All OFF All OFF All OFF All OFF All OFF All OFF LPUART All OFF All OFF All OFF All OFF All OFF All OFF LPSPI All OFF All OFF All OFF All OFF All OFF All OFF LPI2C All OFF All OFF All OFF All OFF All OFF All OFF EMAC/GMAC OFF OFF OFF OFF OFF OFF eMIOS All OFF All OFF All OFF All OFF All OFF All OFF SAR_ADC All OFF All OFF All OFF All OFF All OFF All OFF LPCMP All OFF All OFF All OFF All OFF All OFF All OFF 1. See clocking use case examples in the Clocking chapter of the S32K3xx Reference Manual. Table 22. RUN mode configuration options MODU LE Min. Config. (Optio nF1), PLL@ Min. Config. (Optio nB1), PLL@ Min. Config. (Optio nA1), PLL@ Min. Config. (Optio nA+1), PLL@ Min. Config. (Optio nA+ +1), PLL@ Config. 1 Dual Core Config. 2 Single Core Config. 3 Dual Core Config. 4 Single Core Config. 5 Single Core Config. 6-1 Dual Core Config. 6-2 Triple Core Config. 7 1xLS + 3x Table continues on the next page... NXP Semiconductors Power management S32K3xx Data Sheet, Rev. 9.1, 03/2024 Data Sheet: Technical Data Preliminary Information for S32K388 58 / 143 |
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