S32K311NHT0MPAST datasheet(92/143 Pages) NXP

92 / 143 page

Table 44. LPSPI (continued)

Symbol

Description

Min

Typ

Max

Unit

Condition

Spec

Number

tRI/FI

Rise/Fall time

input 11

—

Master

tRI/FI

Rise/Fall time

input 4,11

—

Master Loopback

1. tperiph = 1/fperiph

2. For LPSPI0 instance, max. peripheral frequency is equal to AIPS_PLAT_CLK.

3. fperiph = LPSPI peripheral clock

4. Master Loopback mode: In this mode LPSPI_SCK clock is delayed for sampling the input data which is enabled by setting

LPSPI_CFGR1[SAMPLE] bit as 1.

5. These specifications apply to the SPI operation, as master or slave, at up to 10 Mbps for the combinations not indicated

in the table below. Unless otherwise noted, all other ‘master’ and ‘slave’ specifications are also applicable in the 10Mbps

configurations. See table "LPSPI 20 MHz and 15 MHz Combinations.

6. LPSPI0 support up to 20MHz on fast pin.

7. Minimum configuration value for CR[PCSSCK] field is 3(0x00000011).

8. Minimum configuration value for CCR[SCKPCS] field is 3(0x00000011).

9. While selecting odd dividers, ensure Duty Cycle is meeting this parameter.

10. Output rise/fall time is determined by the output load and GPIO pad drive strength setting. See the GPIO specifications for

detail.

11. The input rise/fall time specification applies to both clock and data, and is required to guarantee related timing parameters.

SLAVE MSB OUT

SLAVE LSB OUT

BIT 6 ... 1

(INPUT)

SPSCK

(CPOL = 0)

(INPUT)

SPSCK

(CPOL = 1)

(INPUT)

MOSI

(INPUT)

MISO

(OUTPUT)

LSB IN

MSB IN

Figure 42. LPSPI Slave Mode Timing (CPHA=1)

NXP Semiconductors

Communication interfaces

S32K3xx Data Sheet, Rev. 9.1, 03/2024

Data Sheet: Technical Data

Preliminary Information for S32K388

92 / 143

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