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S32K311NHT0MPAST Datasheet(PDF) 86 Page - NXP Semiconductors |
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S32K311NHT0MPAST Datasheet(HTML) 86 Page - NXP Semiconductors |
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86 / 143 page  Table 41. PLL (continued) Symbol Description Min Typ Max Unit Condition Spec Number JPLL_acc PLL accumulated jitter (pk-pk) 1,2,3 — — 840 ps FPLL_out = 120MHz, Integer Mode — JPLL_acc PLL accumulated jitter (pk-pk) 1,2,3 — — 1680 ps FPLL_out = 120MHz, Fractional Mode — 1. For SSCG, jitter due to systematic modulation needs to be added as per applied modulation. Accumulated jitter specification?is not valid with SSCG 2. Jitter numbers calculated by extrapolating RMS jitter numbers to +/- 7 sigma . 3. Jitter numbers are valid only at IP boundary and does not include any degradation due to IO pad for clock measurement. 11.4 FXOSC Table 42. FXOSC Symbol Description Min Typ Max Unit Condition Spec Number FREQ_BYPASS Input clock frequency in bypass mode 1 — — 50 MHz — — TRF_BYPASS Input clock rise/fall time in bypass mode 1 — — 5 ns — — CLKIN_DUTY_ BYPASS Input clock duty cycle in bypass mode 1 47.5 — 52.5 % — — FXOSC_CLK output clock frequency in crystal mode 8 — 40 MHz — — TFXOSC Fxosc start up time (ALC enabled) 2 — — 2 ms — — IFXOSC Oscillator Analog circuit supply current, V25 supply (ALC enable) — — 1 mA using 8, 16 or 40 MHz crystal — IFXOSC Oscillator Analog circuit supply current, V25 supply (ALC disabled) — — 2.7 mA using 8, 16 or 40 MHz crystal — EXTAL_SWING_ PP Peak-to-peak voltage swing on EXTAL pin in crystal oscillator mode (ALC enabled) 0.3 — 1.4 V — — Table continues on the next page... NXP Semiconductors Clocking modules S32K3xx Data Sheet, Rev. 9.1, 03/2024 Data Sheet: Technical Data Preliminary Information for S32K388 86 / 143 |
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