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S32K311NHT0MPAST Datasheet(PDF) 7 Page - NXP Semiconductors |
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S32K311NHT0MPAST Datasheet(HTML) 7 Page - NXP Semiconductors |
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7 / 143 page  Xbar (64 bit) Fabric 2 MB Pflash with ECC Memory 1 x QuadSPI Up to 480 Mbps 4 bit data width External Memory IF 1 x Ethernet, 100 Mbps AVB/TSN 4 x FlexCAN all ch support CAN FD 4 x LPUART (LIN) Network Communication 128 kB Dflash with ECC 256 kB RAM with ECC Include 192 kB TCM FXOSC (8-40 MHz) Memory OTA ready - RWW, A/B swap External Flash/Ram expansion by QuadSPI • • CPU Platform Two independent Arm M7 cores Optimized for Real- time with zero wait I/D-TCM • • Motor Control On-chip motor control subsystem Offloading CPU • • Future Proof Security/OTA ISO26262 Compliant Safety System Scalable Arm platform Optimized for LOW power Rich Network/Communication Interface • • • • • Safety HW redundancy MBIST/LBIST/Self Test Clock/Voltage monitor Centralized error detection ASIL B compliant • • • • • Security HW accl for AES 256, RSA 4096, ECC 521 Firmware included, upgradable Side-channel physical protection Meet Evita Full function goal • • • • Network/ Communication Ethernet (TSN), CAN/ CAN FD, LIN SAI for Audio Flexible IO emulation • • • System FIRC (48 MHz) CPU Platform Cortex-M7 160 MHz FPU, DSP I-cache D-cache Cortex-M7 160 MHz FPU, DSP I-cache D-cache Dual Core SIRC (32 kHz) SXOSC (32 kHz) PLL 32ch DMA 32ch ext. INT/WKUP Analog/Timers BCTU (Body Control Trigger Unit) 2 x 24 ch 12 bit ADC LCU (Logic Control Unit) 2 x 24 ch 16 bit eMIOS Timer 2 x LPCMP Functional Safety CMU FCCU MPU SWT EIM/ERM STCU2 CRC Security: HSE-B Cortex-M0+ RAM XRDC Access control Lifecycle Management Asymmetric Hardware Accelerators Symmetric Hardware Accelerators TRNG/PRNG Debug/Trace (SWD/JTAG/ETB) 32 ch FlexIO Emulating UART, I2C, SPI I2S, SENT, PWM 4 x LPSPI 2 x LPI2C 2 x SAI (TDM, I2S) 32 bit RTC Figure 4. S32K322: ASIL B Dual Core 2MB General Purpose MCU Xbar (64 bit) Fabric 1 MB Pflash with ECC Memory 1 x QuadSPI Up to 480 Mbps 4 bit data width External Memory IF 1 x Ethernet, 100 Mbps AVB/TSN 4 x FlexCAN all ch support CAN FD 4 x LPUART (LIN) Network Communication 128 kB Dflash with ECC 256 kB RAM with ECC Include 192 kB TCM FXOSC (8-40 MHz) Memory OTA ready - RWW, A/B swap External Flash/Ram expansion by QuadSPI • • CPU Platform Scalable Arm M7 core in Lockstep Optimized for Real- time with zero wait I/D-TCM • • Motor Control On-chip motor control subsystem Offloading CPU • • Future Proof Security/OTA ISO26262 Compliant Safety System Scalable Arm platform Optimized for LOW power Rich Network/Communication Interface • • • • • Safety HW redundancy MBIST/LBIST/Self Test Clock/Voltage monitor Centralized error detection ASIL D compliant • • • • • Security HW accl for AES 256, RSA 4096, ECC 521 Firmware included, upgradable Side-channel physical protection Meet Evita Full function goal • • • • Network/ Communication Ethernet (TSN), CAN/ CAN FD, LIN SAI for Audio Flexible IO emulation • • • System FIRC (48 MHz) CPU Platform Cortex-M7 160 MHz FPU, DSP I-cache D-cache Lockstep Core SIRC (32 kHz) SXOSC (32 kHz) PLL 32ch DMA 32ch ext. INT/WKUP Analog/Timers BCTU (Body Control Trigger Unit) 2 x 24 ch 12 bit ADC LCU (Logic Control Unit) 2 x 24 ch 16 bit eMIOS Timer 2 x LPCMP Functional Safety CMU FCCU MPU SWT EIM/ERM STCU2 CRC Security: HSE-B Cortex-M0+ RAM XRDC Access control Lifecycle Management Asymmetric Hardware Accelerators Symmetric Hardware Accelerators TRNG/PRNG Debug/Trace (SWD/JTAG/ETB) 32 ch FlexIO Emulating UART, I2C, SPI I2S, SENT, PWM 4 x LPSPI 2 x LPI2C 2 x SAI (TDM, I2S) Cortex-M7 160 MHz FPU, DSP I-cache D-cache 32 bit RTC Figure 5. S32K341: ASIL D Lockstep Core 1MB General Purpose MCU NXP Semiconductors Block diagram S32K3xx Data Sheet, Rev. 9.1, 03/2024 Data Sheet: Technical Data Preliminary Information for S32K388 7 / 143 |
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