S32K311NHT0MPAST datasheet(87/143 Pages) NXP

87 / 143 page

Table 42. FXOSC (continued)

Symbol

Description

Min

Typ

Max

Unit

Condition

Spec

Number

EXTAL_SWING_

Peak-to-peak

voltage swing on

EXTAL pin in crystal

oscillator mode (ALC

disabled) 3

1.2

—

2.75

—

CLKIN_VIL_

EXTAL_BYPASS

Input clock low level

in bypass mode

—

vref-0.5

vref=0.5*VDD_HV_A

—

CLKIN_VIH_

EXTAL_BYPASS

Input clock high level

in bypass mode

vref+0.5

—

VDD_HV

vref=0.5*VDD_HV_A

—

VSB

Self Bias Voltage

350

—

850

—

Amplifier

Transconductance

9.7

—

18.5

mA/V

GM_SEL[3:0] =

4`b1111

—

1. For bypass mode applications, the EXTAL pin should be driven low when FXOSC is in off/disabled state.

2. The startup time specification is valid only when the recommended crystal and load capacitors are used. For higher load

capacitances, the actual startup time might be higher.

3. The recommended gm setting to ensure extal swing < 2.75V at 8MHz in ALC-disabled mode is gm=4'b0010.

Recommended gm settings in ALC-disabled mode for all other supported frequencies and crystals remain the same.

To ensure stable oscillations, FXOSC incorporates the feedback resistance internally.

Drive level is a crystal specification and if crystal load capacitance is increased beyond the recommended value, it may violate

the crystal drive level rating. In such cases, contact NXP sales representative for selecting the correct crystal.

Crystal oscillator circuit provides stable oscillations when gmXOSC > 5 * gm_crit. The gm_crit is defined as:

gm_crit = 4 * (ESR + RS) * (2πF)2 * (C0 + CL)2

where:

• gmXOSC is the transconductance of the internal oscillator circuit

• ESR is the equivalent series resistance of the external crystal

• RS is the series resistance connected between XTAL pin and external crystal for current limitation

• F is the external crystal oscillation frequency

• C0 is the shunt capacitance of the external crystal

• CL is the external crystal total load capacitance. CL = Cs+ [C1*C2/(C1+C2)]

• Cs is stray or parasitic capacitance on the pin due to any PCB traces

• C1, C2 external load capacitances on EXTAL and XTAL pins

See manufacture datasheet for external crystal component values

Figure 40. Oscillation build-up equation

To improve the FXOSC & PLL jitter performance in S32K328, S32K338, S32K348, S32K358 the functionality of

the pins (namely - PTG0,PTG3,PTF11,PTF19,PTF30, PMOS_CTRL in BGA289 package) cannot be

toggling edge aligned.

NOTE

To improve the FXOSC jitter & duty cycle performance in S32K310, S32K311, S32K312, S32K322, S32K341

S32K342, S32K314,S32K324 and S32K344, the functionality of the pin next to the Oscillator (namely, PTE14 in

172-HDQFP and PTE3 in 100-HDQFP package) must be limited to static GPIO operation.

NOTE

NXP Semiconductors

Clocking modules

S32K3xx Data Sheet, Rev. 9.1, 03/2024

Data Sheet: Technical Data

Preliminary Information for S32K388

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