JS48F4400P0P3C0 datasheet(33/139 Pages) NUMONYX

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April 2008

Datasheet

309823-10

Numonyx™ StrataFlash® Cellular Memory (M18)

4.4

Signal Descriptions x16C

Table 8:

Signal Descriptions for x16C / x16C AD-Mux / x16C AA/D-Mux Ballout (Sheet 1

of 3)

Symbol

Type

Signal Descriptions

Notes

Address and Data Signals, Non-Mux

A[MAX:0]

Input

ADDRESS: Global device signals.

Shared address inputs for all memory die during Read and Write operations.

• 4-Gbit: AMAX = A27• 128-Mbit: AMAX = A22

• 2-Gbit: AMAX = A26• 64-Mbit: AMAX = A21

• 1-Gbit: AMAX = A25• 32-Mbit: AMAX = A20

• 512-Mbit: AMAX = A24• 16-Mbit: AMAX = A19

• 256-Mbit: AMAX = A23• 8-Mbit: AMAX = A18

Unused address inputs should be treated as RFU.

DQ[15:0]

Input /

Output

DATA INPUT/OUTPUTS: Global device signals.

Inputs data and commands during Write cycles, outputs data during Read cycles. Data signals

are High-Z when the device is deselected or its output is disabled.

ADV#

Input

ADDRESS VALID: Flash- and Synchronous PSRAM-specific signal; low-true input.

During synchronous flash Read operations, the address is latched on the rising edge of F-ADV#,

or on the first rising edge of F-CLK after F-ADV# goes low for devices that support up to 108

MHz, or on the last rising edge of F-CLK after F-ADV# goes low for devices that support up to

133 MHz.

In an asynchronous flash Read operation, the address is latched on the rising edge of ADV# or

continuously flows through while ADV# is low.

Address and Data Signals, AD-Mux

A[MAX:16]

Input

ADDRESS: Global device signals.

Shared address inputs for all memory die during Read and Write operations.

• 4-Gbit: AMAX = A27• 128-Mbit: AMAX = A22

• 2-Gbit: AMAX = A26• 64-Mbit: AMAX = A21

• 1-Gbit: AMAX = A25• 32-Mbit: AMAX = A20

• 512-Mbit: AMAX = A24• 16-Mbit: AMAX = A19

• 256-Mbit: AMAX = A23• 8-Mbit: AMAX = A18

Unused address inputs should be treated as RFU.

AD[15:0]

Input /

Output

ADDRESS-DATA MULTIPLEXED INPUTS/ OUTPUTS: Global device signals.

During AD-Mux Write cycles, AD[15:0] are used to input the lower address followed by

commands or data. During AD-Mux Read cycles, AD[15:0] are used to input the lower address

followed by read-data output.

During NAND accesses, AD[7:0] is used to input commands, address-data, or write-data, and

output read-data.

AD[15:0] are High-Z when the device is deselected or its output is disabled.

ADV#

Input

ADDRESS VALID: Flash- and Synchronous PSRAM-specific signal; low-true input.

During synchronous flash Read operations, the address is latched on the rising edge of F-ADV#,

or on the first rising edge of F-CLK after F-ADV# goes low for devices that support up to 108

MHz, or on the last rising edge of F-CLK after F-ADV# goes low for devices that support up to

133 MHz.

In an asynchronous flash Read operation, the address is latched on the rising edge of ADV#.

Address and Data Signals, AAD-Mux

AD[15:0]

Input /

Output

ADDRESS-DATA MULTIPLEXED INPUTS/ OUTPUTS: Global device signals.

During AAD-Mux flash Write cycles, AD[15:0] are used to input the upper address, lower

address, and commands or data. During AAD-Mux flash Read cycles, AD[15:0] are used to

input the upper address and lower address, and output read-data.

During NAND accesses, AD[7:0] is used to input commands, address-data, or write-data, and

output read-data.

AD[15:0] are High-Z when the device is deselected or its output is disabled.

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