JS48F4400P0P3C0 datasheet(40/139 Pages) NUMONYX

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Numonyx™ StrataFlash® Cellular Memory (M18)

Datasheet

April 2008

309823-10

N-R/B#

Output

NAND READY/BUSY: NAND-specific signal; low-true output.

• When low, N-RY/BY# indicates the NAND device is busy performing a read, program, or

erase operations.

• When high, N-RY/BY# indicates the NAND device is ready.

N-RE#

Output

NAND READ ENABLE: NAND-specific signal; drives the data onto the flash bus after the falling

edge of N-RE#.

This signal increments the internal column address and reads out each data.

D-CKE

Input

LPSDRAM CLOCK ENABLE: LPSDRAM-specific signal; high-true input.

• When high, D-CKE indicates that the next D-CLK edge is valid.

• When low, D-CKE indicates that the next D-CLK edge is invalid and the selected LPSDRAM

die is suspended.

D-BA[1:0]

Input

LPSDRAM BANK SELECT: LPSDRAM-specific input signals.

D-BA[1:0] selects one of four banks in the LPSDRAM die.

D-RAS#

Input

LPSDRAM ROW ADDRESS STROBE: LPSDRAM-specific signal; low-true input.

D-RAS#, together with A[MAX:0], D-BA[1:0], D-CKE, D-CS#, D-CAS#, and D-WE#, define

the LPSDRAM command or operation. D-RAS# is sampled on the rising edge of D-CLK.

D-CAS#

Input

LPSDRAM COLUMN ADDRESS STROBE: LPSDRAM-specific signal; low-true input.

D-CAS#, together with A[MAX:0], D-BA[1:0], D-CKE, D-CS#, D-RAS#, and D-WE#, define

the LPSDRAM command or operation. D-CAS# is sampled on the rising edge of D-CLK.

D[2:1]-CE#

Input

LPSDRAM CHIP ENABLE: LPSDRAM-specific signal; low-true input.

When low, D-CS# selects the associated LPSDRAM memory die and starts the command input

cycle.

When D-CS# is high, commands are ignored but operations continue.

• D-CS#, together with A[MAX:0], D-BA[1:0], D-CKE, D-RAS#, D-CAS#, and D-WE#,

define the LPSDRAM command or operation. D-CS# is sampled on the rising edge of D-

CLK.

• D[2:1]-CS# are dedicated to LPSDRAM die #2 and die #1, respectively, if present.

Otherwise, treat any unused LPSDRAM chip selects as RFU.

D-DM[1:0]

Input

LPSDRAM DATA MASK: LPSDRAM-specific signal; high-true input.

When high, D-DM[1:0] controls masking of input data during writes and output data during

reads.

• D-DM1 corresponds to the data on DQ[15:8].

• D-DM0 corresponds to the data on DQ[7:0].

D-DQS1

D-DQS0

Input /

Output

LPSDRAM UPPER/LOWER DATA STROBE: DDR LPSDRAM-specific input/output signals.

D-DQS1 and D-DQS0 provide as output the read data strobes, and as input the write data

strobes.

• D-DQS1 corresponds to the data on DQ[15:8].

• D-DQS0 corresponds to the data on DQ[7:0].

S-CS1#

S-CS2#

Input

SRAM CHIP SELECTS: SRAM-specific signals.

• S-CS1# low-true input.

• S-CS2# high-true input.

• When both are asserted, S-CS1# and S-CS2 select the SRAM die.

• When either is deasserted, the SRAM die is deselected and its power is reduced to

standby levels.

S-UB#

S-LB#

Input

SRAM UPPER/LOWER BYTE ENABLES: SRAM-specific signals; low-true inputs.

• When low, S-UB# enables DQ[15:8] and S-LB# enables DQ[7:0] during SRAM read and

write cycles.

• When high, S-UB# masks DQ[15:8] and S-LB# masks DQ[7:0].

2,3

Power Signals

F-VPP

Power

FLASH PROGRAM/ERASE VOLTAGE: Flash specific.

F-VPP supplies program or erase power to the flash die.

Table 9:

Signal Descriptions, x16 Split Bus, Non-Mux (Sheet 3 of 4)

Symbol

Type

Signal Descriptions

Notes

JS48F4400P0P3C0 Datasheet(PDF) 40 Page - Numonyx B.V

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