JS48F4400P0P3C0 datasheet(39/139 Pages) NUMONYX

39 / 139 page

April 2008

Datasheet

309823-10

Numonyx™ StrataFlash® Cellular Memory (M18)

F-ADV#

Input

FLASH ADDRESS VALID: Flash-specific signal; low-true input.

During synchronous flash Read operations, the address is latched on the rising edge of F-

ADV#, or on the first rising edge of F-CLK after F-ADV# goes low for devices that support up

to 108 MHz, or on the last rising edge of F-CLK after F-ADV# goes low for devices that support

up to 133 MHz.

In an asynchronous flash Read operation, the address is latched on the rising edge of F-ADV#.

F[4:1]-CE#

Input

FLASH CHIP ENABLE: Flash-specific signal; low-true input.

When low, F-CE# selects the associated flash memory die.

When high, F-CE# deselects the associated flash die. Flash die power is reduced to standby

levels, and its data and F-WAIT outputs are placed in a High-Z state.

• F1-CE# is dedicated to flash die #1.

• F[4:2]-CE# are dedicated to flash die #4 through #2, respectively, if present. Otherwise,

treat any unused flash chip enable as RFU.

• When NAND is used, F4-CE# is dedicated for NAND die 1 and NAND die 2. Otherwise, this

is RFU.

F-CLK

Input

FLASH CLOCK: Flash-specific signal; configurable active-edge input.

F-CLK synchronizes the flash memory with the system clock during synchronous operations.

D-CLK

Input

LPSDRAM CLOCK: LPSDRAM-specific signal; rising active-edge input.

D-CLK synchronizes the LPSDRAM and DDR LPSDRAM with the system clock.

D-CLK#

Input

DDR LPSDRAM CLOCK: DDR LPSDRAM-specific signal; falling active-edge input.

D-CLK# synchronizes the DDR LPSDRAM with the system clock.

F-OE#

Input

FLASH OUTPUT ENABLE: Flash-specific signal; low-true input.

• When low, OE# enables the output drivers of the selected flash die.

• When high, OE# disables the output drivers of the selected flash die and places the

output drivers in High-Z.

F-RST#

Input

FLASH RESET: Flash-specific signal; low-true input.

• When low, F-RST# resets internal operations and inhibits writes.

• When high, F-RST# enables normal operation.

F-WAIT

Output

FLASH WAIT: Flash-specific signal; configurable-true output.

When asserted, F-WAIT indicates invalid output data.

• F-WAIT is driven whenever F-CE# and OE# is low.

• F-WAIT is High-Z whenever F-CE# or OE# is high.

F-WE#

Input

FLASH WRITE ENABLE: Flash-specific signal; low-true input.

When low, WE# enables write operations for the selected flash die.

N-WE#

Input

NAND WRITE ENABLE: NAND-specific signal; low-true input.

When low, WE# enables write operations for the selected NAND die.

D-WE#

Input

LPSDRAM WRITE ENABLE: LPSDRAM-specific signal; low-true input.

D-WE#, together with A[MAX:0], D-BA[1:0], D-CKE, D-CS#, D-CAS#, and D-RAS#, define

the LPSDRAM command or operation. D-WE# is sampled on the rising edge of D-CLK.

F-WP[2:1]#

Input

FLASH WRITE PROTECT: Flash-specific signals; low-true inputs.

When low, F-WP# enables the Lock-Down mechanism.

When high, F-WP# overrides the Lock-Down function, enabling locked-down blocks to be

unlocked with the Unlock command.

• F-WP1# is dedicated to flash die #1.

• F-WP2# is used for NAND die when available. Otherwise, this signal is for all other NOR

die.

F-DPD

Input

FLASH DEEP POWER-DOWN: Flash-specific signal; configurable-true input.

When enabled in the ECR, F-DPD is used to enter or exit Deep Power-Down mode.

N-CLE

Input

NAND COMMAND LATCH ENABLE: NAND-specific signal; high-true input.

When high, N-CLE enables commands to be latched on the rising edge of WE#.

N-ALE

Input

NAND ADDRESS LATCH ENABLE: NAND-specific signal; high-true input.

When high, N-ALE enables addresses to be latched on the rising edge of WE#.

Table 9:

Signal Descriptions, x16 Split Bus, Non-Mux (Sheet 2 of 4)

Symbol

Type

Signal Descriptions

Notes

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