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JS48F4400P0P3C0 Datasheet(PDF) 97 Page - Numonyx B.V

Part # JS48F4400P0P3C0
Description  StrataFlash짰 Cellular Memory
PDF  139 Pages
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Manufacturer  NUMONYX [Numonyx B.V]
Direct Link  http://www.numonyx.com
Logo NUMONYX - Numonyx B.V

JS48F4400P0P3C0 Datasheet(HTML) 97 Page - Numonyx B.V

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April 2008
Datasheet
309823-10
97
Numonyx™ StrataFlash® Cellular Memory (M18)
Notes:
1.
[n,n,n] denotes logical state of WP#, DQ1,and DQ0, respectively; X = Don’t Care.
2.
[0,1,1] states should be tracked by system software to differentiate between the Hardware-Locked state and the Lock-
Down state.
9.11.2
One-Time Programmable (OTP) Registers
The device contains seventeen 128-bit One-Time Programmable (OTP) Registers, and
twoa 16-bit OTP Lock Registers, as shown in Figure 50, “2-Kbit OTP Registers” on
page 98. The OTP Lock Register 0 is used for locking the OTP Register 0, and OTP Lock
Register 1 is used for locking OTP Registers 1 through 16.
The OTP Register 0 consists of two 64-bit segments: a lower segment that is pre-
programmed with a unique 64-bit value and locked at the factory; and an upper
segment that contains all “ones” and is user-programmable. OTP Registers 1 through
16 contain all “ones” and are user-programmable.
Figure 49: Block Locking Operations
Locked
[X,0,1]
Unlocked
[X,0,0]
Locked
Down
2
[0,1,1]
Power Up
-or-
Exit from Reset
Software
Locked
[1,1,1]
Hardware
Locked
2
[0,1,1]
Unlocked
[1,1,0]
WP# = VIL
WP# = VIH
Software Control(Lock, Unlock, Lock-Down Command)
Hardware Control(WP#)



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