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JS48F4400P0P3C0 Datasheet(PDF) 60 Page - Numonyx B.V |
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JS48F4400P0P3C0 Datasheet(HTML) 60 Page - Numonyx B.V |
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60 / 139 page  Numonyx™ StrataFlash® Cellular Memory (M18) Datasheet April 2008 60 309823-10 7.3 Write Specifications The M18 device includes specifications for different lithographies, densities, and frequencies. For additional information on combinations, see Table 4, “M18 Product Litho/Density/Frequency Combinations” on page 10 in the Section 2.0, “Functional Description. Table 22: AC Write Specifications Number Symbol Parameter (1, 2) Min Max Units Notes W1 tPHWL RST# high recovery to WE# low 150 — ns 1,2,3 W2 tELWL CE# setup to WE# low 0 — ns 1,2 W3 tWLWH WE# write pulse width low 40 — ns 1,2,4 W4 tDVWH Data setup to WE# high 40 — ns 1,2 W5 tAVWH Address setup to WE# high 40 — ns W6 tWHEH CE# hold from WE# high 0 — ns W7 tWHDX Data hold from WE# high 0 — ns W8 tWHAX Address hold from WE# high (non-mux only) 0 — ns W9 tWHWL WE# pulse width high 20 — ns 1,2,5 W10 tVPWH VPP setup to WE# high 200 — ns 1,2,3,7 W11 tQVVL VPP hold from Status read 0 — ns W12 tQVBL WP# hold from Status read 0 — ns W13 tBHWH WP# setup to WE# high 200 — ns W14 tWHGL WE# high to OE# low 0 — ns 1,2,8 W15 tVLWH ADV# low to WE# high (AD-Mux only) 55 — ns 1,2 W16 tWHQV WE# high to read valid tAVQV+30 — ns 1,2,3,9 Write to Synchronous Read Specifications W19 tWHCH WE# high to Clock high 15 — ns 1,2,3,6,9 W27 tWHEL WE# high to CE# low 9 — ns 1,2,3,6,9 W28 tWHVL WE# high to ADV# low 7 — ns 1,2,3,6,9 Bus Write with Active Clock Specifications W21 tVHWL ADV# high to WE# low — 27 ns 1,2,10,11 W22 tCHWL Clock high to WE# low — 27 ns Notes: 1. Write timing characteristics during erase suspend are the same as write-only operations. 2. A write operation can be terminated with either CE# or WE#. 3. Sampled, not 100% tested. 4. Write pulse width low (tWLWH or tELEH) is defined from CE# or WE# low (whichever occurs last) to CE# or WE# high (whichever occurs first). Hence, tWLWH = tELEH = tWLEH = tELWH. 5. Write pulse width high (tWHWL or tEHEL) is defined from CE# or WE# high (whichever occurs first) to CE# or WE# low (whichever occurs last). Hence, tWHWL = tEHEL = tWHEL = tEHWL). 6. tWHCH must be met when transitioning from a write cycle to a synchronous burst read. In addition there must be a CE# toggle after WE# goes high. 7. VPP and WP# should be at a valid level until erase or program success is determined. 8. When doing a Read Status operation following any command that alters the Status Register data, W14 is 20ns. 9. Add 10ns if the write operations results in a RCR or block lock status change, for the subsequent read operation to reflect this change. 10. This specification is applicable only if the part is configured in synchronous mode and an active clock is running. Either tVHWL or tCHWL must be met depending on the whether the address is latched on ADV# or CLK. 11. These specifications are not applicable to 133 MHz devices. |
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