JS48F4400P0P3C0 datasheet(35/139 Pages) NUMONYX

35 / 139 page

April 2008

Datasheet

309823-10

Numonyx™ StrataFlash® Cellular Memory (M18)

N-ALE

Input

NAND ADDRESS LATCH ENABLE: NAND-specific signal; high-true input.

When high, N-ALE enables addresses to be latched on the rising edge of N-WE#.

N-RE#

Input

NAND READ ENABLE: NAND-specific signal; low-true input.

When low, N-RE# enables the output drivers of the selected NAND die. When high, N-RE#

disables the output drivers of the selected NAND die and places the output drivers in High-Z.

1, 2

N-RY/BY#

Output

NAND READY/BUSY: NAND-specific signal; low-true output.

When low, N-RY/BY# indicates the NAND is busy performing a Read, Program, or Erase

operation. When high, N-RY/BY# indicates the NAND device is ready.

N-WE#

Input

NAND WRITE ENABLE: NAND-specific signal; low-true input.

When low, N-WE# enables Write operations for the enabled NAND die.

1, 4

P-CRE

Input

PSRAM CONTROL REGISTER ENABLE: Synchronous PSRAM-specific signal; high-true input.

When high, P-CRE enables access to the Refresh Control Register (P-RCR) or Bus Control

1, 3

P-MODE#

Input

PSRAM MODE#: Asynchronous only PSRAM-specific signal; low-true input.

When low, P-MODE# enables access to the configuration register, and to enter or exit Low-

Power mode. When high, P-MODE# enables normal Read or Write operations.

1, 3

P[2:1]-CS#

Input

PSRAM CHIP SELECT: PSRAM-specific signal; low-true input.

When low, P-CS# selects the associated PSRAM memory die. When high, P-CS# deselects the

associated PSRAM die. PSRAM die power is reduced to standby levels, and its data and WAIT

outputs are placed in a High-Z state.

• P1-CS# is dedicated to PSRAM die #1.

• P2-CS# IS dedicated to PSRAM die #2. Otherwise, any unused PSRAM chip select should be

treated as RFU.

S-CS1#

S-CS2

Input

SRAM CHIP SELECTS: SRAM-specific signals; S-CS1# low-true input, S-CS2 high-true input.

When both S-CS1# and S-CS2 are asserted, the SRAM die is selected. When either S-CS1# or

S-CS2 is deasserted, the SRAM die is deselected.

1, 4

R-UB#

R-LB#

Input

RAM UPPER/LOWER BYTE ENABLES: PSRAM- and SRAM-specific signals; low-true inputs.

When low, R-UB# enables DQ[15:8] and R-LB# enables DQ[7:0] during PSRAM or SRAM Read

and Write cycles. When high, R-UB# masks DQ[15:8] and R-LB# masks DQ[7:0].

Power Signals

F-VPP

Power

FLASH PROGRAM/ERASE VOLTAGE: Flash specific.

F-VPP supplies program or erase power to the flash die.

F[2:1]-VCC

Power

FLASH CORE POWER SUPPLY: Flash specific.

F[2:1]-VCC supplies the core power to the flash die.

For NOR/NAND stacked device, F1-VCC is dedicated for all NOR dies, F2-VCC is dedicated for all

NAND dies.

VCCQ

Power

I/O POWER SUPPLY: Global device I/O power.

VCCQ supplies the device input/output driver voltage.

P-VCC

Power

PSRAM CORE POWER SUPPLY: PSRAM specific.

P-VCC supplies the core power to the PSRAM die.

S-VCC

Power

SRAM POWER SUPPLY: SRAM specific.

S-VCC supplies the core power to the SRAM die.

VSS

Groun

DEVICE GROUND: Global ground reference for all signals and power supplies.

Connect all VSS balls to system ground. Do not float any VSS connections.

—

DO NOT USE:

Ball should not be connected to any power supplies, signals, or other balls. Ball can be left

floating.

RFU

—

RESERVED for FUTURE USE:

Reserved by Numonyx for future device functionality and enhancement. Ball must be left

floating.

Table 8:

Signal Descriptions for x16C / x16C AD-Mux / x16C AA/D-Mux Ballout (Sheet 3

of 3)

Symbol

Type

Signal Descriptions

Notes

JS48F4400P0P3C0 Datasheet(PDF) 35 Page - Numonyx B.V

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