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JS48F4400P0P3C0 Datasheet(PDF) 69 Page - Numonyx B.V

Part # JS48F4400P0P3C0
Description  StrataFlash짰 Cellular Memory
PDF  139 Pages
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Manufacturer  NUMONYX [Numonyx B.V]
Direct Link  http://www.numonyx.com
Logo NUMONYX - Numonyx B.V

JS48F4400P0P3C0 Datasheet(HTML) 69 Page - Numonyx B.V

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April 2008
Datasheet
309823-10
69
Numonyx™ StrataFlash® Cellular Memory (M18)
7.5
Reset Specifications
7.6
Deep Power Down Specifications
Table 25: Reset Specifications
Nbr.
Symbol
Parameter
Min
Max
Unit
Notes
P1
tPLPH
RST# pulse width low
100
ns
1,2,3,4,7
P2
tPLRH
RST# low to device reset during erase
—
25
µs
1,3,4,7
RST# low to device reset during program
—
25
1,3,4,7
P3
tVCCPH
VCC Power valid to RST# de-assertion (high)
300
—
1,4,5,6
Notes:
1.
These specifications are valid for all device versions (packages and speeds).
2.
The device may reset if tPLPH is < tPLPH MIN, but this is not guaranteed.
3.
Not applicable if RST# is tied to Vccq.
4.
Sampled, but not 100% tested.
5.
If RST# is tied to the VCC supply, device will not be ready until tVCCPH after VCC ≥ VCC min.
6.
If RST# is tied to any supply/signal with VCCQ voltage levels, the RST# input voltage must not exceed VCC until VCC ≥
VCC(min).
7.
Reset completes within tPLPH if RST# is asserted while no erase or program operation is executing.
Figure 40: Reset Operation Timing
(A) Reset during
read mode
(B) Reset during
program or block erase
P1
≤ P2
(C) Reset during
program or block erase
P1
≥ P2
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
RST# [P]
RST# [P]
RST# [P]
Abort
Complete
Abort
Complete
V
CC
0V
V
CC
(D) VCC Power-up to
RST# high
P1
R5
P2
P3
P2
R5
R5
Table 26: Deep Power Down Specifications (Sheet 1 of 2)
Nbr.
Symbol
Parameter
Min
Max
Unit
Notes
S1
tSLSH (tSHSL)
DPD asserted pulse width
100
—
ns
1,2,3



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