JS48F4400P0P3C0 datasheet(78/139 Pages) NUMONYX

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Numonyx™ StrataFlash® Cellular Memory (M18)

Datasheet

April 2008

309823-10

Upon power-up or exit from reset, the Read Configuration Register defaults to

asynchronous mode (RCR15 = 1; RCR[14:11] and RCR[9:0] are ignored).

To read the RCR value, issue the Read Device Information command to the desired

partition. Subsequent reads from the <partition base address> + 05h will output

RCR[15:0] on the data bus.

When using a Latency Count of Code 2 and a Data Hold of two cycles (CR9 = 1), WAIT

must be configured to deassert with valid data (CR8 = 0).

9.2.1

Latency Count

The Latency Count value programmed into RCR[14:11] is the number of valid CLK

edges from address-latch to the start of the data-output delay. When the Latency

Count has been satisfied, output data is driven after tCHQV.

Table 31: Read Configuration Register Bit Definitions

Read Configuration Register (RCR)

Default: CR15 = 1

Read

Mode

Latency Count

WAIT

Polarity

WAIT

Delay

Reserved

Burst Length

7:3

Bit

Name

Description

Read Mode

0 = Synchronous burst-mode reads

1 = Asynchronous page-mode reads (default)

14:11

Latency Count

Bits: 141312 11

001 1= 3

010 0= 4

010 1= 5

011 0= 6

011 1= 7

100 0= 8

100 1= 9

101 0= 10

101 1= 11

110 0= 12

(Other bit settings are reserved)

WAIT Polarity

0 = WAIT signal is active low (default)

1 = WAIT signal is active high

Reserved

Write 0 to reserved bits

8WAIT Delay

0 = WAIT de-asserted with valid data

1 = WAIT de-asserted one cycle before valid data (default)

7:3

Reserved

Write 0 to reserved bits

2:0

Burst Length

010= 8-word burst (wrap only)

011= 16-word burst (wrap only)

111= Continuous-word burst (no-wrap; default) (Other bit settings

are reserved)

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