JS48F4400P0P3C0 datasheet(34/139 Pages) NUMONYX

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Numonyx™ StrataFlash® Cellular Memory (M18)

Datasheet

April 2008

309823-10

F-ADV2#

ADV#

Input

FLASH ADDRESS VALID: Flash-specific signal; low-true input.

During AAD-Mux flash accesses, the upper address is latched on the valid edge of CLK while

F-ADV2# is low; the lower address is latched on the valid edge of CLK while ADV# is low.

The upper address is always latched first, followed by the lower address.

Control Signals

F[4:1]-CE#

Input

FLASH CHIP ENABLE: Flash-specific signal; low-true input.

When low, F-CE# selects the associated flash memory die. When high, F-CE# deselects the

associated flash die. Flash die power is reduced to standby levels, and its data and F-WAIT

outputs are placed in a High-Z state.

• F1-CE# is dedicated to flash die #1.

• F[4:2]-CE# are dedicated to flash die #4 through #2, respectively, if present. Otherwise,

any unused flash chip enable should be treated as RFU.

• For NOR/NAND stacked device, F1-CE# selects NOR die #1, F2-CE# selects NOR die #2

while F4-CE# selects NAND die #1 and NAND die #2 using virtual chip-select scheme, F3-

CE# selects NAND die #3 if present.

CLK

Input

CLOCK: Flash- and Synchronous PSRAM-specific input signal.

CLK synchronizes the flash and/or synchronous PSRAM with the system clock during

synchronous operations.

F[2:1]-OE#

Input

FLASH OUTPUT ENABLE: Flash-specific signal; low-true input.

When low, F-OE# enables the output drivers of the selected flash die. When high, F-OE#

disables the output drivers of the selected flash die and places the output drivers in High-Z.

• For NOR only stacked device, F[2:1]-OE# are common to all NOR dies in the device.

• For NOR/NAND stacked device, F1-OE# enables all NOR dies, F2-OE# selects all NAND dies

if present.

R-OE#

Input

RAM OUTPUT ENABLE: PSRAM- and SRAM-specific signal; low-true input.

When low, R-OE# enables the output drivers of the selected memory die. When high, R-OE#

disables the output drivers of the selected memory die and places the output drivers in High-Z.

F-RST#

Input

FLASH RESET: Flash-specific signal; low-true input.

When low, F-RST# resets internal operations and inhibits writes. When high, F-RST# enables

normal operation.

WAIT

Output

WAIT: Flash -and Synchronous PSRAM-specific signal; configurable true-level output.

When asserted, WAIT indicates invalid output data. When deasserted, WAIT indicates valid

output data.

• WAIT is driven whenever the flash or the synchronous PSRAM is selected and its output

enable is low.

• WAIT is High-Z whenever flash or the synchronous PSRAM is deselected, or its output

enable is high.

F-WE#

Input

FLASH WRITE ENABLE: Flash-specific signal; low-true input.

When low, F-WE# enables Write operations for the enabled flash die. Address and data are

latched on the rising edge of F-WE#.

R-WE#

Input

RAM WRITE ENABLE: PSRAM- and SRAM-specific signal; low-true input.

When low, R-WE# enables Write operations for the selected memory die. Data is latched on the

rising edge of R-WE#.

F-WP[2:1]#

Input

FLASH WRITE PROTECT: Flash-specific signals; low-true inputs.

When low, F-WP# enables the Lock-Down mechanism. When high, F-WP# overrides the Lock-

Down function, enabling locked-down blocks to be unlocked with the Unlock command.

• F-WP1# is dedicated to flash die #1.

• F-WP2# is common to all other flash dies, if present. Otherwise it is RFU.

• For NOR/NAND stacked device, F-WP1# selects all NOR dies, while F-WP2# selects all

NAND dies.

F-DPD

Input

FLASH DEEP POWER-DOWN: Flash-specific signal; configurable-true input.

When enabled in the ECR, F-DPD is used to enter and exit Deep Power-Down mode.

N-CLE

Input

NAND COMMAND LATCH ENABLE: NAND-specific signal; high-true input.

When high, N-CLE enables commands to be latched on the rising edge of N-WE#.

Table 8:

Signal Descriptions for x16C / x16C AD-Mux / x16C AA/D-Mux Ballout (Sheet 2

of 3)

Symbol

Type

Signal Descriptions

Notes

JS48F4400P0P3C0 Datasheet(PDF) 34 Page - Numonyx B.V

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