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JS48F4400P0P3C0 Datasheet(PDF) 51 Page - Numonyx B.V

Part # JS48F4400P0P3C0
Description  StrataFlash짰 Cellular Memory
PDF  139 Pages
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Manufacturer  NUMONYX [Numonyx B.V]
Direct Link  http://www.numonyx.com
Logo NUMONYX - Numonyx B.V

JS48F4400P0P3C0 Datasheet(HTML) 51 Page - Numonyx B.V

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April 2008
Datasheet
309823-10
51
Numonyx™ StrataFlash® Cellular Memory (M18)
R303
tELCH
CE# low setup to CLK high
5
—
ns
—
R304
tCHQV
CLK to output valid
—
7
ns
—
R305
tCHQX
Output hold from CLK high
2
—
ns
—
R306
tCHAX
Address hold from CLK high
5
—
ns
4
R307
tCHTV
CLK high to WAIT valid
—
7
ns
—
R311
tCHVL
CLK high to ADV# Setup
2
—
ns
—
R312
tCHTX
WAIT hold from CLK
2
—
ns
—
Notes:
1.
See
Figure 18, “AC Input/Output Reference Waveform” on page 48 for timing measurements and
maximum allowable input slew rate.
2.
OE# may be delayed by up to tELQV – tGLQV after CE#’s falling edge without impact to tELQV.
3.
Sampled, not 100% tested.
4.
Address hold in synchronous burst mode is tCHAX or tVHAX, whichever timing specification is satisfied first.
Table 19: AC Read, 108 MHz, VCCQ = 1.7 V to 2.0 V (Sheet 2 of 2)
Nbr.
Symbol
Parameter1
96 ns
Unit
Notes
Min
Max
Table 20: AC Read, 133 MHz, VCCQ = 1.7 V to 2.0 V (Sheet 1 of 2)
Nbr.
Symbol
Parameter1
96 ns
Units
Notes
Min
Max
Asynchronous Specifications
R1
tAVAV
Read cycle time
96
—
ns
—
R2
tAVQV
Address to output valid
—
96
ns
—
R3
tELQV
CE# low to output valid
—
96
ns
—
R4
tGLQV
OE# low to output valid
—
7
ns
2
R5
tPHQV
RST# high to output valid
—
150
ns
—
R6
tELQX
CE# low to output in low-Z
0
—
ns
3
R7
tGLQX
OE# low to output in low-Z
0
—
ns
2,3
R8
tEHQZ
CE# high to output in high-Z
—
7
ns
3
R9
tGHQZ
OE# high to output in high-Z
—
7
ns
R10
tOH
Output hold from first occurring address, CE#, or OE# change
0
—
ns
R11
tEHEL
CE# pulse width high
7
—
ns
—
R12
tELTV
CE# low to WAIT valid
—
8
ns
—
R13
tEHTZ
CE# high to WAIT high Z
—
7
ns
3
R14
tGHTV
OE# high to WAIT valid (AD-Mux only)
—
5.5
ns
—
R15
tGLTV
OE# low to WAIT valid
—
5.5
ns
—
R16
tGLTX
OE# low to WAIT in low-Z
0
—
ns
3
R17
tGHTZ
OE# high to WAIT in high-Z (non-mux only)
0
7
ns
3
Latching Specifications
R101
tAVVH
Address setup to ADV# high
5
—
ns
—
R102
tELVH
CE# low to ADV# high
7
—
ns
—
R103
tVLQV
ADV# low to output valid
96
ns
—



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