RA4C1 datasheet(38/97 Pages) RENESAS

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2.3.3

Reset Timing

Table 2.28

Reset timing

Parameter

Symbol

Min

Typ

Max

Unit

Test

conditions

RES pulse width

At power-on

tRESWP

—

Figure 2.12

Not at power-on

tRESW

—

µs

Figure 2.13

Wait time after RES cancellation (at

power-on)

LVD0 enabled*1

tRESWT

—

1.0

—

Figure 2.12

LVD0 disabled*2

—

0.3

—

Wait time after RES cancellation (during

powered-on state)

LVD0 enabled*1

tRESWT2

—

0.9

—

Figure 2.13

LVD0 disabled*2

—

0.2

—

Wait time after internal reset

cancellation (IWDT reset, WDT reset,

RAM parity error reset, RAM ECC error

reset, Bus master MPU error reset,

TrustZonre error reset, Cache parity

error reset, Software reset)

LVD0 enabled*1

tRESWT3

—

0.9

—

Figure 2.14

LVD0 disabled*2

—

0.2

—

Note 1. When OFS1.LVDAS = 0.

Note 2. When OFS1.LVDAS = 1.

VCC

RES

tRESWP

Internal reset

tRESWT

Figure 2.12

Reset input timing at power-on

RES

Internal reset

tRESWT2

tRESW

Figure 2.13

Reset input timing (1)

RA4C1 Datasheet

2. Electrical Characteristics

R01DS0457EJ0110 Rev.1.10

Jul 4, 2025

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