RA4C1 datasheet(4/97 Pages) RENESAS

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Table 1.6

External bus interface

Feature

Functional description

External bus

● QSPI area (EQBIU): Connected to the QSPI (external device interface)

Table 1.7

Timers

Feature

Functional description

General PWM Timer (GPT)

The General PWM Timer (GPT) is a 32-bit timer with GPT32 × 2 channels and a 16-bit timer

with GPT16 × 4 channels. PWM waveforms can be generated by controlling the up-counter,

down-counter, or the up- and down-counter. In addition, PWM waveforms can be generated for

controlling brushless DC motors. The GPT can also be used as a general-purpose timer.

Port Output Enable for GPT (POEG)

The Port Output Enable (POEG) function can place the General PWM Timer (GPT) output pins

in the output disable state.

Low Power Asynchronous General

Purpose Timer (AGT)

The low power Asynchronous General Purpose Timer (AGT) is a 32-bit timer that can be used

for pulse output, external pulse width or period measurement, and counting external events. This

timer consists of a reload register and a down counter. The reload register and the down counter

are allocated to the same address, and can be accessed with the AGT register.

Realtime Clock (RTC)

The Realtime Clock (RTC) has two operation modes, normal operation mode and low-

consumption clock mode. In each of the operation mode, the RTC has two counting modes,

calendar count mode and binary count mode, that are used by switching register settings. For

calendar count mode, the RTC has a 100-year calendar from 2000 to 2099 and automatically

adjusts dates for leap years. For binary count mode, the RTC counts seconds and retains the

information as a serial value. Binary count mode can be used for calendars other than the

Gregorian (Western) calendar.

Watchdog Timer (WDT)

The Watchdog Timer (WDT) is a 14-bit down counter that can be used to reset the MCU when

the counter underflows because the system has run out of control and is unable to refresh the

WDT. In addition, the WDT can be used to generate a non-maskable interrupt or an underflow

interrupt.

Independent Watchdog Timer (IWDT)

The Independent Watchdog Timer (IWDT) consists of a 14-bit down counter that must be

serviced periodically to prevent counter underflow. The IWDT provides functionality to reset

the MCU or to generate a non-maskable interrupt or an underflow interrupt. Because the timer

operates with an independent, dedicated clock source, it is particularly useful in returning the

MCU to a known state as a fail-safe mechanism when the system runs out of control. The IWDT

can be triggered automatically by a reset, underflow, refresh error, or a refresh of the count value

in the registers.

Table 1.8

Communication interfaces (1 of 2)

Feature

Functional description

Serial Communications Interface (SCI)

The Serial Communications Interface (SCI) × 6 channels have asynchronous and synchronous

serial interfaces:

● Asynchronous interfaces (UART and Asynchronous Communications Interface Adapter

(ACIA))

● 8-bit clock synchronous interface

● Simple IIC (master-only)

● Simple SPI

● Smart card interface

● Manchester interface

● Simple LIN

The smart card interface complies with the ISO/IEC 7816-3 standard for electronic signals and

transmission protocol. SCIn (n = 0, 3 to 5, 9) has FIFO buffers to enable continuous and

full-duplex communication, and the data transfer speed can be configured independently using

an on-chip baud rate generator.

IrDA Interface

The IrDA interface sends and receives IrDA data communication waveforms in cooperation with

the SCI5 based on the IrDA (Infrared Data Association) standard 1.0.

I2C bus interface (IIC)

The I2C bus interface (IIC) has two channels. The IIC module conforms with and provides a

subset of the NXP I2C (Inter-Integrated Circuit) bus interface functions.

Serial Interface UARTA (UARTA)

The serial interface UARTA (UARTA) has two channels. The UARTA supports the following

modes:

● Operation stop mode

● UART mode

RA4C1 Datasheet

1. Overview

R01DS0457EJ0110 Rev.1.10

Jul 4, 2025

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