RA4C1 datasheet(52/97 Pages) RENESAS

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Table 2.40

SPI timing (2 of 3)

Parameter

Symbol

Min

Max

Unit

Test conditions

Data input setup

time

Master

2.7 V ≤ VCC ≤ 3.6 V

tSU

—

Figure 2.33 to

Figure 2.38

C = 30 pF

2.4 V ≤ VCC < 2.7 V

—

1.8 V ≤ VCC < 2.4 V

—

1.6 V ≤ VCC < 1.8 V

—

Slave

2.4 V ≤ VCC ≤ 3.6 V

—

1.8 V ≤ VCC < 2.4 V

—

1.6 V ≤ VCC < 1.8 V

—

Data input hold

time

Master (RSPCK is PCLKA/2)

tHF

—

Master (RSPCK is not PCLKA/2)

tPcyc

—

Slave

—

SSL setup time

Master

1.8 V ≤ VCC ≤ 3.6 V

tLEAD

−30 + N × tSpcyc*1

—

1.6 V ≤ VCC < 1.8 V

−34 + N × tSpcyc*1

—

Slave

5 × tPcyc

—

SSL hold time

Master

tLAG

−30 + N × tSpcyc*2

—

Slave

5 × tPcyc

—

Data output

delay time

Master

2.7 V ≤ VCC ≤ 3.6 V

tOD

—

2.4 V ≤ VCC < 2.7 V

—

1.8 V ≤ VCC < 2.4 V

—

1.6 V ≤ VCC < 1.8 V

—

Slave

2.7 V ≤ VCC ≤ 3.6 V

—

2.4 V ≤ VCC < 2.7 V

—

1.8 V ≤ VCC < 2.4 V

—

1.6 V ≤ VCC < 1.8 V

—

Data output hold

time

Master

tOH

—

Slave

—

Successive

transmission

delay time

Master

tTD

tSPcyc + 2 × tPcyc

8 × tSPcyc + 2 ×

tPcyc

Slave

6 × tPcyc

—

MOSI and MISO

rise and fall time

Output

2.7 V ≤ VCC ≤ 3.6 V

tDr, tDf

—

Figure 2.33 to

Figure 2.38

C = 30 pF

2.4 V ≤ VCC < 2.7 V

—

1.8 V ≤ VCC < 2.4 V

—

1.6 V ≤ VCC < 1.8 V

—

Input

—

SSL rise and fall

time

Output

2.7 V ≤ VCC ≤ 3.6 V

tSSLr,

tSSLf

—

2.4 V ≤ VCC < 2.7 V

—

1.8 V ≤ VCC < 2.4 V

—

1.6 V ≤ VCC < 1.8 V

—

Input

—

RA4C1 Datasheet

2. Electrical Characteristics

R01DS0457EJ0110 Rev.1.10

Jul 4, 2025

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