RA4C1 datasheet(46/97 Pages) RENESAS

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Table 2.37

SCI timing (1) (2 of 2)

Conditions: VCC = AVCC0 = 1.6 to 3.6 V

Parameter

Symbol

Min

Max

Unit

Test

conditions

SCI

Receive data

setup time

(master)

Clock

synchronous

1.8 V ≤ VCC ≤ 3.6 V

tRXS

—

Figure 2.25

2.4 V ≤ VCC < 2.7 V

—

1.8 V ≤ VCC < 2.4 V

—

1.6 V ≤ VCC < 1.8 V

—

Receive data

setup time (slave)

Clock

synchronous

2.4 V ≤ VCC ≤ 3.6 V

—

1.8 V ≤ VCC ≤ 2.4 V

—

1.6 V ≤ VCC < 1.8 V

—

Receive data hold

time (master)

Clock synchronous

tRXH

—

Receive data hold

time (slave)

Clock synchronous

tRXH

—

tSCKW

tSCKr

tSCKf

tScyc

SCKn

Note:

n = 0, 1, 3 to 5, 9

Figure 2.24

SCK clock input timing

tTXD

tRXS tRXH

TXDn

RXDn

SCKn

Note:

n = 0, 1, 3 to 5, 9

Figure 2.25

SCI input/output timing in clock synchronous mode

RA4C1 Datasheet

2. Electrical Characteristics

R01DS0457EJ0110 Rev.1.10

Jul 4, 2025

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