RA4C1 datasheet(2/97 Pages) RENESAS

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Overview

The MCU integrates multiple series of software- and pin-compatible Arm®-based 32-bit cores that share a common set of

Renesas peripherals to facilitate design scalability and efficient platform-based product development.

The MCU in this series incorporates a high-performance Arm Cortex®-M33 core running up to 80 MHz with the following

features:

● Up to 512 KB code flash memory

● 96 KB SRAM

● Quad Serial Peripheral Interface (QSPI)

● Analog peripherals

● Security and safety features

1.1

Function Outline

Table 1.1

Arm core

Feature

Functional description

Arm Cortex-M33 core

● Maximum operating frequency: up to 80 MHz

● Arm Cortex-M33 core:

– Armv8-M architecture with security extension

– Revision: r0p4-00rel1

● Arm Memory Protection Unit (Arm MPU)

– Protected Memory System Architecture (PMSAv8)

– Secure MPU (MPU_S): 8 regions

– Non-secure MPU (MPU_NS): 8 regions

● SysTick timer

– Embeds two Systick timers: Secure and Non-secure instance

– Driven by SysTick timer clock (SYSTICCLK) or system clock (ICLK)

● CoreSight™ ETM-M33

Table 1.2

Memory

Feature

Functional description

Code flash memory

Maximum 512 KB of code flash memory.

Data flash memory

8 KB of data flash memory.

Option-setting memory

The option-setting memory determines the state of the MCU after a reset.

SRAM

On-chip high-speed SRAM with either parity bit or Error Correction Code (ECC).

Table 1.3

System (1 of 2)

Feature

Functional description

Operating modes

Two operating modes:

● Single-chip mode

● SCI/SWD boot mode

Resets

The MCU provides 13 resets.

RA4C1 Datasheet

1. Overview

R01DS0457EJ0110 Rev.1.10

Jul 4, 2025

Page 2 of 97

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