RA4C1 datasheet(60/97 Pages) RENESAS

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Table 2.43

IIC timing (2)

Conditions: VCC = AVCC0 = 2.7 to 3.6 V

Parameter

Symbol

Min*1

Max*1

Unit

Test conditions

IIC

(Fast-mode+)

ICFER.FMPE = 1

SCL input cycle time

tSCL

6 (12) × tIICcyc +

240

—

Figure 2.41

SCL input high pulse width

tSCLH

3 (6) × tIICcyc + 120 —

SCL input low pulse width

tSCLL

3 (6) × tIICcyc + 120 —

SCL, SDA rise time

tSr

—

120

SCL, SDA fall time

tSf

—

120

SCL, SDA input spike pulse

removal time

tSP

1 (4) × tIICcyc

SDA input bus free time when

wakeup function is disabled

tBUF

3 (6) × tIICcyc + 120 —

SDA input bus free time when

wakeup function is enabled

tBUF

3 (6) × tIICcyc + 4 ×

tPcyc + 120

—

Start condition input hold time

when wakeup function is disabled

tSTAH

tIICcyc + 120

—

START condition input hold time

when wakeup function is enabled

tSTAH

1 (5) × tIICcyc +

tPcyc + 120

—

Restart condition input setup time

tSTAS

120

—

Stop condition input setup time

tSTOS

120

—

Data input setup time

tSDAS

tIICcyc + 30

—

Data input hold time

tSDAH

—

SCL, SDA capacitive load

Cb*2

—

550

Note:

tIICcyc: IIC internal reference clock (IICφ) cycle, tPcyc: PCLKB cycle.

Note:

The Fast-mode Plus enable bit (FMPE) is supported by IIC0 (SCL0_A, SDA0_A) and IIC1 (SCL1_A, SDA1_A).

Note 1. Values in parentheses apply when ICMR3.NF[1:0] is set to 11b while the digital filter is enabled with ICFER.NFE set to 1.

Note 2. Cb indicates the total capacity of the bus line.

SDAn

SCLn

VIH

VIL

tSTAH

tSCLH

tSCLL

P*1

S*1

tSf

tSr

tSCL

tSDAH

tSDAS

tSTAS

tSP

tSTOS

P*1

tBUF

Sr*1

Note:

n = 0, 1

Note 1. S, P, and Sr indicate the following conditions:

S: Start condition

P: Stop condition

Sr: Restart condition

Figure 2.41

I2C bus interface input/output timing

RA4C1 Datasheet

2. Electrical Characteristics

R01DS0457EJ0110 Rev.1.10

Jul 4, 2025

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