RA4C1 datasheet(43/97 Pages) RENESAS

43 / 97 page

tIRQW

IRQ

Figure 2.18

IRQ interrupt input timing

2.3.6

I/O Ports, POEG, GPT, AGT, and ADC12 Trigger Timing

Table 2.35

I/O Ports, POEG, GPT, AGT, and ADC12 trigger timing

Parameter

Symbol

Min

Max

Unit

Test

conditions

I/O Ports

Input data pulse width

2.7 V ≤ VCC ≤ 5.5 V

tPRW

—

tPcyc

Figure 2.19

2.4 V ≤ VCC < 2.7 V

1.6 V ≤ VCC < 2.4 V

POEG

POEG input trigger pulse width

tPOEW

—

tPcyc

Figure 2.20

GPT

Input capture pulse width

Single edge

tGTICW

1.5

—

tPDcyc

Figure 2.21

Dual edge

2.5

—

AGT

AGTIO, AGTEE input cycle

1.8 V ≤ VCC ≤ 5.5 V

tACYC*1

250

—

Figure 2.22

1.6 V ≤ VCC < 1.8 V

2000

—

AGTIO, AGTEE input high-level

width, low-level width

1.8 V ≤ VCC ≤ 5.5 V

tACKWH,

tACKWL

100

—

1.6 V ≤ VCC < 1.8 V

800

—

AGTIO, AGTO, AGTOA,

AGTOB output cycle

2.7 V ≤ VCC ≤ 5.5 V

tACYC2

62.5

—

Figure 2.22

2.4 V ≤ VCC < 2.7 V

125

—

1.8 V ≤ VCC < 2.4 V

250

—

1.6 V ≤ VCC < 1.8 V

500

—

ADC12

12-bit A/D converter trigger input pulse width

tTRGW

1.5

—

tPcyc

Figure 2.23

Note 1. Constraints on AGTIO input: tPcyc × 2 (tPcyc: PCLKB cycle) < tACYC.

Port

tPRW

Figure 2.19

I/O ports input timing

POEG input trigger

tPOEW

Figure 2.20

POEG input trigger timing

RA4C1 Datasheet

2. Electrical Characteristics

R01DS0457EJ0110 Rev.1.10

Jul 4, 2025

Page 43 of 97

RA4C1 Datasheet(PDF) 43 Page - Renesas Technology Corp

RA4C1 Datasheet(HTML) 43 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97

Datasheet Download

Link URL