RA4C1 datasheet(94/97 Pages) RENESAS

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Table A3.2

Access cycles (2 of 3)

Peripherals

Address

Number of access cycles

ICLK = PCLK

ICLK > PCLK*1

Cycle

Unit

Related function

From

Read

Write

Read

Write

CRC, DOC

0x4010_8000

0x4010_9FFF

2 to 5

2 to 4

PCLKA

CRC Calculator, Data

Operation Circuit

SCIn

0x4011_8000

0x4011_8FFF

5*3

4*3

2 to 5*3

2 to 4*3

PCLKA

Serial Communication

Interface n

SPIn

0x4011_A000

0x4011_AFFF

5*4

4*4

2 to 5*4

2 to 4*4

PCLKA

Serial Peripheral

Interface n

ECCMB

0x4011_F000

0x4012_FFFF

2 to 5

2 to 4

PCLKA

Error correction circuit

for MBRAM

GPT32n, GPT16n,

GPT_OPS

0x4016_9000

0x4016_9FFF

4 to 7

2 to 4

PCLKA

General PWM 32-Bit

Timer n, General

PWM 16-Bit Timer

n, Output Phase

Switching Controller

ADC120

0x4017_0000

0x4017_1FFF

2 to 5

2 to 4

PCLKA

12bit A/D Converter 0

QSPI

0x6400_0000

0x6400_000F

14 to *5

2 to 5

14 to *5

PCLKA

Quad-SPI

QSPI

0x6400_0010

0x6400_0013

25 to *5

6 to *5

25 to *5

5 to *5

PCLKA

Quad-SPI

QSPI

0x6400_0014

0x6400_0037

14 to *5

2 to 5

14 to *5

PCLKA

Quad-SPI

QSPI

0x6400_0804

0x6400_0807

1 to 4

1 to 3

PCLKA

Quad-SPI

Table A3.2

Access cycles (3 of 3)

Peripherals

Address

Number of access cycles

ICLK = FCLK

ICLK > FCLK*1

Cycle

Unit

Related function

From

Read

Write

Read

Write

FLCN, FACI

0x407E_C000

0x407F_EFFF

3 to 5

2 to 4

FCLK

Flash I/O Registers,

Flash Application

Command Interface

Note 1. If the number of PCLK or FCLK cycles is non-integer (for example 1.5), the minimum value is without the decimal point, and the

maximum value is rounded up to the decimal point. For example, 1.5 to 2. 5 is 1 to 3.

Note 2. The access cycles of the PRCNT2 and PFS registers depend on PRWCNTR.

Note 3. When accessing a 16-bit register (FTDRHL, FRDRHL, FCR, FDR, LSR, and CDR), access is 2 cycles more than the value shown in

Table A3.2. When accessing an 8-bit register (including FTDRH, FTDRL, FRDRH, and FRDRL), the access cycles are as shown in

Table A3.2.

Note 4. When accessing the 32-bit register (SPDR), access is 2 cycles more than the value in Table A3.2. When accessing an 8-bit or 16-bit

Note 5. The access cycles depend on the QSPI bus cycles.

RA4C1 Datasheet

Appendix 3. I/O Registers

R01DS0457EJ0110 Rev.1.10

Jul 4, 2025

Page 94 of 97

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