RA4C1 datasheet(93/97 Pages) RENESAS

93 / 97 page

● In the internal I/O area, reserved addresses that are not allocated to registers must not be accessed, otherwise operations

cannot be guaranteed.

● The number of I/O access cycles depends on bus cycles of the internal peripheral bus, divided clock synchronization

cycles, and wait cycles of each module. Divided clock synchronization cycles differ depending on the frequency ratio

between ICLK and PCLK.

● When the frequency of ICLK is equal to that of PCLK, the number of divided clock synchronization cycles is always

constant.

● When the frequency of ICLK is greater than that of PCLK, at least 1 PCLK cycle is added to the number of divided

clock synchronization cycles.

● The number of write access cycles indicates the number of cycles obtained by non-bufferable write access.

Note:

This applies to the number of cycles when access from the CPU does not conflict with the instruction fetching to the

external memory or bus access from other bus masters such as DTC or DMAC.

Table A3.2

Access cycles (1 of 3)

Peripherals

Address

Number of access cycles

ICLK = PCLK

ICLK > PCLK*1

Cycle

Unit

Related function

From

Read

Write

Read

Write

RMPU, TZF,

SRAM, BUS,

DMACn, DMA,

DTC, ICU

0x4000_0000

0x4000_6FFF

ICLK

Renesas Memory

Protection Unit,

TrustZone Filter,

SRAM Control,

BUS Control, Direct

memory access

controller n, DMAC

Module Activation,

DTC Control Register,

Interrupt Controller

CACHE

0x4000_7000

0x4000_7FFF

ICLK

CACHE

CPSCU, DBG,

FCACHE

0x4000_8000

0x4001_CFFF

ICLK

CPU System Security

Control Unit, Debug

Function, Flash Cache

SYSC

0x4001_E000

0x4001_E5FF

ICLK

System Control

PORTn, PFS

0x4001_F000

0x4001_FFFF

5*2

ICLK

Port n Control

Registers, Pmn Pin

Function Control

ELC, RTC, IWDT,

WDT, CAC, MSTP,

POEG

0x4008_2000

0x4008_AFFF

2 to 5

2 to 4

PCLKB

Event Link

Controller, Realtime

Clock, Independent

Watchdog Timer,

Watchdog

Timer, Clock

Frequency Accuracy

Measurement Circuit,

Module Stop Control,

Port Output Enable

Module for GPT

UARTA

0x4009_7000

0x4009_7FFF

1 to 4

1 to 3

PCLKB

Serial Interface

UARTA

IICn, IIC0WU,

CANFD

0x4009_D000

0x400D_0FFF

2 to 5

2 to 4

PCLKB

Serial Sound Interface

Enhanced, Inter-

Integrated Circuit n,

Inter-Integrated Circuit

0 Wake-up Unit,

CANFD Module

SLCDC

0x400D_4000

0x400D_4FFF

1 to 4

1 to 3

PCLKB

Segment LCD

Controller/Driver

PSCU

0x400E_0000

0x400E_0FFF

2 to 5

2 to 4

PCLKB

Peripheral Security

Control Unit

AGTn

0x400E_8000

0x400E_8FFF

4 to 7

2 to 4

PCLKB

Low Power

Asynchronous

General purpose

Timer n

RA4C1 Datasheet

Appendix 3. I/O Registers

R01DS0457EJ0110 Rev.1.10

Jul 4, 2025

Page 93 of 97

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