RA4C1 datasheet(81/97 Pages) RENESAS

81 / 97 page

Table 2.67

Internal voltage boosting method LCD characteristics (3) (2 of 2)

Conditions: VCC = AVCC = VL2 (Max) + 0.1 to 3.6 V, VSS = AVSS = 0 V

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

Test conditions

LCD output voltage

variation range

VL2

C1 to C4*1 = 0.47

µF

VLCD*2 = 0x84

1.94

2.02

2.11

—

VLCD = 0x85

2.00

2.09

2.18

—

VLCD = 0x86

2.07

2.16

2.25

—

VLCD = 0x87

2.13

2.22

2.32

—

VLCD = 0x88

2.19

2.29

2.39

—

VLCD = 0x89

2.26

2.36

2.46

—

VLCD = 0x8A

2.32

2.42

2.53

—

VLCD = 0x8B

2.39

2.49

2.59

—

VLCD = 0x8C

2.45

2.56

2.66

—

VLCD = 0x8D

2.51

2.62

2.73

—

VLCD = 0x8E

2.58

2.69

2.80

—

VLCD = 0x8F

2.64

2.76

2.87

—

VLCD = 0x90

2.70

2.82

2.94

—

VLCD = 0x91

2.77

2.89

3.01

—

VLCD = 0x92

2.83

2.96

3.08

—

VLCD = 0x93

2.90

3.02

3.15

—

VLCD = 0x94

2.96

3.09

3.22

—

VLCD = 0x95

3.02

3.15

3.29

—

VLCD = 0x96

3.09

3.22

3.35

—

VLCD = 0x97

3.15

3.29

3.42

—

VLCD = 0x98

3.21

3.35

3.49

—

VLCD = 0x99

3.28

3.42

3.56

—

VLCD = 0x9A

3.34

3.49

3.63

—

Two-thirds output

voltage

VL4*5

C1 to C4*1 = 0.47 µF

2/3 ×

VL2 - 6%

2/3 ×

VL2

2/3 ×

VL2 +

—

Reference voltage

setup time*3

tVL2S

—

Figure 2.56

Voltage boost wait

time*4

tVLWT

—

500

—

Figure 2.56

Note:

0x8E to 0x9A setting is permitted when using 5V LCD panel, 0x84 to 0x87 setting is permitted when using 3V LCD panel at 1/3

bias.

Note 1. This is a capacitor that is connected between the voltage pins that are used to drive the LCD.

C1: A capacitor connected between CAPH and CAPL

C2: A capacitor connected between VL1 and GND

C3: A capacitor connected between VL2 and GND

C4: A capacitor connected between VL4 and GND

C1 = C2 = C3 = C4 = 0.47 µF ±30%

Note 2. Bit [7] (MDSET[2]) of register VLCD is set to 1 and bits [7:6] (MDSET[1:0]) of register LCDM0 are set to 01 for internal voltage

boosting method (VL2 reference), and bits [4:0] (VLCD4-0) of register VLCD are used for voltage variation setting.

Note 3. This is the time required to wait from when the reference voltage is specified by using the VLCD register (or when the internal

voltage boosting method is selected (by setting the MDSET[1:0] bits of the LCDM0 register to 01b and MDSET[2] of the register

VLCD to 1) if the default value reference voltage is used) until voltage boosting starts (VLCON = 1).

Note 4. This is the wait time from when voltage boosting is started (VLCON = 1) until display is enabled (LCDON = 1).

Note 5. VL4 must be 3.6 V or lower.

RA4C1 Datasheet

2. Electrical Characteristics

R01DS0457EJ0110 Rev.1.10

Jul 4, 2025

Page 81 of 97

RA4C1 Datasheet(PDF) 81 Page - Renesas Technology Corp

RA4C1 Datasheet(HTML) 81 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97

Datasheet Download

Link URL