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RA4C1 Datasheet(PDF) 86 Page - Renesas Technology Corp |
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RA4C1 Datasheet(HTML) 86 Page - Renesas Technology Corp |
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86 / 97 page  Table 2.77 Data flash characteristics (4) (2 of 2) Low-speed operating mode Conditions: VCC = AVCC0 = 1.6 to 3.6 V Parameter Symbol ICLK = 1 MHz Unit Min Typ Max Data flash STOP recovery time tDSTOP 250 — — ns Note: Does not include the time until each operation of the flash memory is started after instructions are executed by software. Note: The lower-limit frequency of FCLK is 1 MHz during programming or erasing the flash memory. Note: The frequency accuracy of FCLK must be ± 1.0% during programming or erasing the flash memory. Confirm the frequency accuracy of the clock source. 2.13.3 Serial Wire Debug (SWD) Table 2.78 SWD characteristics (1) Conditions: VCC = AVCC0 = 2.4 to 5.5 V Parameter Symbol Min Typ Max Unit Test conditions SWCLK clock cycle time tSWCKcyc 50 — — ns Figure 2.57 SWCLK clock high pulse width tSWCKH 15 — — ns SWCLK clock low pulse width tSWCKL 15 — — ns SWCLK clock rise time tSWCKr — — 5 ns SWCLK clock fall time tSWCKf — — 5 ns SWDIO setup time tSWDS 3 — — ns Figure 2.58 SWDIO hold time tSWDH 13 — — ns SWDIO data delay time tSWDD 2 — 45 ns Table 2.79 SWD characteristics (2) Conditions: VCC = AVCC0 = 1.6 to 2.4 V Parameter Symbol Min Typ Max Unit Test conditions SWCLK clock cycle time tSWCKcyc 250 — — ns Figure 2.57 SWCLK clock high pulse width tSWCKH 120 — — ns SWCLK clock low pulse width tSWCKL 120 — — ns SWCLK clock rise time tSWCKr — — 5 ns SWCLK clock fall time tSWCKf — — 5 ns SWDIO setup time tSWDS 50 — — ns Figure 2.58 SWDIO hold time tSWDH 50 — — ns SWDIO data delay time tSWDD 2 — 170 ns tSWCKH tSWCKf tSWCKcyc SWCLK tSWCKr tSWCKL Figure 2.57 SWD SWCLK timing RA4C1 Datasheet 2. Electrical Characteristics R01DS0457EJ0110 Rev.1.10 Jul 4, 2025 Page 86 of 97 |
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