RA4C1 datasheet(85/97 Pages) RENESAS

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addresses in 256-byte blocks, and then the entire block is erased, the reprogram/erase cycle is counted as one. However,

programming the same address for several times as one erasure is not enabled. (overwriting is prohibited.)

Note 2. Characteristics when using the flash memory programmer and the self-programming library provided by Renesas Electronics.

Note 3. This result is obtained from reliability testing.

Table 2.75

Data flash characteristics (2)

High-speed operating mode

Conditions: VCC = AVCC0 = 1.8 to 3.6 V

Parameter

Symbol

ICLK = 1 MHz

ICLK = 48 MHz

Unit

Min

Typ

Max

Min

Typ

Max

Programming time

1-byte

tDP1

—

112

903

—

33.9

317

µs

Erasure time

256-byte

tDE256

—

14.1

390

—

5.50

214

Blank check time

1-byte

tDBC1

—

67.7

—

8.6

µs

256-byte

tDBC256

—

7538

—

272

µs

Suspended time during erasing

tDSED

—

33.4

—

10.7

µs

Forced stop time

tFD

—

33.4

—

10.7

µs

Data flash STOP recovery time

tDSTOP

250

—

250

—

Note:

Does not include the time until each operation of the flash memory is started after instructions are executed by software.

Note:

The lower-limit frequency of FCLK is 1 MHz during programming or erasing the flash memory.

Note:

The frequency accuracy of FCLK must be ± 1.0% during programming or erasing the flash memory. Confirm the frequency accuracy

of the clock source.

Table 2.76

Data flash characteristics (3)

Middle-speed operating mode

Conditions: VCC = AVCC0 = 1.6 to 3.6 V

Parameter

Symbol

ICLK = 1 MHz

ICLK = 8 MHz*1

Unit

Min

Typ

Max

Min

Typ

Max

Programming time

1-byte

tDP1

—

112

903

—

39.7

359

µs

Erasure time

256-byte

tDE256

—

14.1

390

—

6.32

231

Blank check time

1-byte

tDBC1

—

67.7

—

13.3

µs

256-byte

tDBC256

—

7538

—

947

µs

Suspended time during erasing

tDSED

—

33.4

—

13.1

µs

Forced stop time

tFD

—

33.4

—

13.1

µs

Data flash STOP recovery time

tDSTOP

250

—

250

—

Note:

Does not include the time until each operation of the flash memory is started after instructions are executed by software.

Note:

The lower-limit frequency of FCLK is 1 MHz during programming or erasing the flash memory.

Note:

The frequency accuracy of FCLK must be ± 1.0% during programming or erasing the flash memory. Confirm the frequency accuracy

of the clock source.

Note 1. When 1.8 V ≤ VCC = AVCC0 ≤ 3.6 V

Table 2.77

Data flash characteristics (4) (1 of 2)

Low-speed operating mode

Conditions: VCC = AVCC0 = 1.6 to 3.6 V

Parameter

Symbol

ICLK = 1 MHz

Unit

Min

Typ

Max

Programming time

1-byte

tDP1

—

112

903

µs

Erasure time

256-byte

tDE256

—

14.1

390

Blank check time

1-byte

tDBC1

—

67.7

µs

256-byte

tDBC256

—

7538

µs

Suspended time during erasing

tDSED

—

33.4

µs

Forced stop time

tFD

—

33.4

µs

RA4C1 Datasheet

2. Electrical Characteristics

R01DS0457EJ0110 Rev.1.10

Jul 4, 2025

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