RA4C1 datasheet(26/97 Pages) RENESAS

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Note 3. ICC depends on f (ICLK) as follows (reference data).

ICC Max. = 0.83 × f + 10.44 (max. operation)

ICC Typ. = 0.16 × f + 0.82 (normal operation, all peripheral clocks disabled and cache disabled)

ICC Typ. = 0.22 × f + 3.64 (Sleep mode, all peripheral clocks enabled and cache disabled)

Note 4. PCLKA, PCLKB, PCLKC, and PCLKD are set to divided by 64 (1.25 MHz).

Note 5. PLL is stopped, and HOCO output frequency = 80 MHz

Note 6. This is the increase for programming or erasure of the flash memory for data storage during program execution.

Table 2.11

Middle-speed mode current

Parameter

Symbol

Typ

Max

Unit

Test conditions

Normal mode

All peripheral clocks enabled, and cache

disabled. While (1) code is executing from flash

ICC*1

4.49

—

ICLK = 8 MHz

PCLKA = 8 MHz

PCLKB = 8 MHz

PCLKC = 8 MHz

PCLKD = 8 MHz

FCLK = 8 MHz

All peripheral clocks disabled, and cache

disabled. While (1) code is executing from

flash*2

1.79

—

Sleep mode

All peripheral clocks enabled, and cache

disabled

3.50

—

All peripheral clocks disabled, and cache

disabled*2

0.81

—

Increase during BGO operation*3

2.10

—

Note:

Supply current is the total current flowing into VCC and VRTC. Supply current values are with all output pins unloaded and all input

pull-up MOSs in the off state.

Note:

This does not include the BGO operation.

Note:

The clock source is MOCO.

Note 1. ICC depends on f (ICLK) as follows (reference data).

ICC Typ. = 0.45 × f + 0.94 (normal operation, all peripheral clocks enabled and cache disabled)

Note 2. PCLKA, PCLKB, PCLKC, and PCLKD are set to divided by 64 (125 kHz).

Note 3. This is the increase for programming or erasure of the flash memory for data storage during program execution.

Table 2.12

Low-speed mode current

Parameter

Symbol

Typ

Max

Unit

Test conditions

Normal mode

All peripheral clocks enabled, and cache

disabled. While (1) code is executing from flash

ICC*1

1.20

—

ICLK = 1 MHz

PCLKA = 1 MHz

PCLKB = 1 MHz

PCLKC = 1 MHz

PCLKD = 1 MHz

FCLK = 1 MHz

All peripheral clocks disabled, and cache

disabled. While (1) code is executing from

flash*2

0.38

—

Sleep mode

All peripheral clocks enabled, and cache

disabled

1.07

—

All peripheral clocks disabled, and cache

disabled*2

0.24

—

Note:

Supply current is the total current flowing into VCC and VRTC. Supply current values are with all output pins unloaded and all input

pull-up MOSs in the off state.

Note:

This does not include the BGO operation.

Note:

The clock source is MOSC.

Note 1. ICC depends on f (ICLK) as follows (reference data).

ICC Typ. = 0.47 × f + 0.43 (normal operation, all peripheral clocks disabled and cache disabled)

Note 2. PCLKA, PCLKB, PCLKC, and PCLKD are set to divided by 64 (15.625 kHz).

Table 2.13

Subosc-speed mode current

Parameter

Symbol

Typ

Max

Unit

Test conditions

Normal mode

All peripheral clocks enabled, and cache

disabled. While (1) code is executing from flash

ICC

18.44

—

µA

ICLK = 32.768 kHz

PCLKA = 32.768 kHz

PCLKB = 32.768 kHz

PCLKC = 32.768 kHz

PCLKD = 32.768 kHz

FCLK = 32.768 kHz

All peripheral clocks disabled, and cache

disabled. While (1) code is executing from

flash*1

9.86

—

Sleep mode

All peripheral clocks enabled, and cache

disabled

13.71

—

All peripheral clocks disabled, and cache

disabled*1

5.17

—

RA4C1 Datasheet

2. Electrical Characteristics

R01DS0457EJ0110 Rev.1.10

Jul 4, 2025

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