7643 datasheet(187/424 Pages) RENESAS

187 / 424 page

Rev.2.00

Aug 28, 2006

page 66 of 202

7643 Group

REJ09B0133-0200

APPLICATION

2.4 UART

Fig. 2.4.30 Connection diagram

UTXD

CTS

P85/URXD

P87/RTS

USB

USB IN

Host PC

7643 Group

Host CPU

DMA transfer

Transmitting side

Receiving side

(4) Data packet transfer (with no error processing) from UART to USB FIFO using DMA

Outline : write the data received from host CPU by UART to USB FIFO by DMA, and transmit the

data to host PC.

Specifications : • USB Endpoint1: IN bulk transfer

• USB Endpoint1: IN interrupt

• USB Endpoint1 packet size: 64 Bytes

• UART receive is used.

• DMA cycle steal transfer mode (fixed address -> fixed address transfer)

• DMA transfer unit : 64 bytes fixed (short packet un-supported)

• UART receive buffer full interrupt request is used for DMA factor

• Transfer bit rate : 9600 bps (

φ = 12 MHz divided by 1248)

In this case, f(XIN)=24 MHz, system clock=f(XIN).

φ is system clock divided by 2.

• Data format: 1ST-8DATA-1SP

• Parity bit is disabled

• Re-transmit by transfer error is not performed

• Use of RTS functions

After the hardware reset, the UART receive and DMA are enabled in the initial setting. The UART

receive interrupt source is set for a trigger of DMA.

When the UART receive is started, the UART receive interrupt source (UART receive buffer full

interrupt and UART receive summing error interrupt are not used) occurs. By this UART receive

interrupt as a trigger of DMA, the 1-byte data of UART transmit/receive buffer register is transferred

to the USB FIFO.

In the 7643 group, DMA interrupt occurs after DMA transfers the 64-byte UART receive data to

USB FIFO. In this time, the DMA is disabled and the IN_PKT_RDY flag of USB Endpoint1 IN is

set to “1.” As a result, the USB Endpoint1 can transmit the data to host PC.

Meanwhile, in the 7643 Group, after the data of USB FIFO is transmitted to host PC, the USB

Endpoint1 IN interrupt occurs. In this time, DMA is set to be enabled again and the DMA transfer

of the next UART receive data to USB FIFO is started.

Figure 2.4.30 shows a connection diagram.

Figure 2.4.31, 2.4.32 and 2.4.33 show register settings.

Figure 2.4.34 and 2.4.35 show control procedures.

7643 Datasheet(PDF) 187 Page - Renesas Technology Corp

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