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7643 Datasheet(PDF) 321 Page - Renesas Technology Corp |
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7643 Datasheet(HTML) 321 Page - Renesas Technology Corp |
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321 / 424 page  Rev.2.00 Aug 28, 2006 page 200 of 202 7643 Group REJ09B0133-0200 APPLICATION 2.10 Clock generating circuit Fig. 2.10.14 Setting of relevant registers after detecting power failure Timer 1 (address 2416) T1 02 Set (Division ratio -1) (T1 = 2 (0216), T2 = 227 (E216) Timer 123 mode register (address 2916) 0 T123M 0 Timer 1 count: Operating 0 1 Timer 1 count source: f(XCIN)/2 Timer 2 count source: Timer 1 output Interrupt control register B (address 0616) ICONB 1 Timer 1 interrupt: Disabled CPU mode register A (address 0016) 1 CPMA 0 1 1 XCIN-XCOUT oscillating 1 XIN-XOUT stopped External clock selected as internal system clock f(XCIN) selected as external clock Timer 1, 2 write: Write value in latch and counter 0 Timer 2 interrupt: Enbled Timer 2 (address 2516) T2 227 b0 b0 b7 b7 b0 b7 b0 b7 b0 b7 00 0 0 0 |
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