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7643 Datasheet(PDF) 317 Page - Renesas Technology Corp |
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7643 Datasheet(HTML) 317 Page - Renesas Technology Corp |
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317 / 424 page ![]() Rev.2.00 Aug 28, 2006 page 196 of 202 7643 Group REJ09B0133-0200 APPLICATION 2.10 Clock generating circuit Fig. 2.10.10 Setting of relevant registers b7 b0 Clock control register (address 1F16) 0 : Middle-speed mode (f(XIN)/2) 1 : High-speed mode (f(XIN)) 0 b7 b0 CCR 00 0 0 CPMA 0 01 01 CPU mode register A (address 0016) Sub-clock f(XCIN) oscillating Main-clock f(XIN) oscillating Main-clock f(XIN) selected b7 b0 CPMA 0 11 11 CPU mode register A (address 0016) Sub-clock f(XCIN) oscillating Main-clock f(XIN) stopped Sub-clock f(XCIN) selected |
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