7643 datasheet(319/424 Pages) RENESAS

319 / 424 page

Rev.2.00

Aug 28, 2006

page 198 of 202

7643 Group

REJ09B0133-0200

APPLICATION

2.10 Clock generating circuit

(2) Counting without clock error during power failure

Outline: It keeps counting without clock error during a power failure.

Specifications: •Reducing power consumption as low as possible while maintaining clock function

•Clock: f(XIN) = 24 MHz

•Sub clock: f(XCIN) = 32.768 kHz

•Use of Timer 2 interrupt

For the peripheral circuit and the status transition during a power failure, refer to Figures 2.10.8

and 2.10.9.

Figure 2.10.12 shows the structure of clock counter, Figures 2.10.13 and 2.10.14 show the setting

of relevant registers.

Fig. 2.10.12 Structure of clock counter

When the system returns from a

power failure, add the time taken

for the switching processing for the

return.

Timer 1 interrupt

1/228

Timer 2

183

µs

1/24

f(XCIN) = 32.768 kHz

1/3

Timer 1

f(XIN) = 24 MHz

Timer 1Base counter1 second counter

1 minute counter

1/8

1/255

1/245

1/24

1/60

1 s

Minute/Time/Day/Month/Year

170

µs

Timer 2 interrupt

: Software timer

: Hardware timer

1/2

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