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7643 Datasheet(PDF) 318 Page - Renesas Technology Corp |
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7643 Datasheet(HTML) 318 Page - Renesas Technology Corp |
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318 / 424 page  Rev.2.00 Aug 28, 2006 page 197 of 202 7643 Group REJ09B0133-0200 APPLICATION 2.10 Clock generating circuit Control procedure: Set the relevant registers in the order shown below to prepare for a power failure. Fig. 2.10.11 Control procedure Initialization CCR (address 1F16) CPMA (address 0016) 100000002 00011XXX2 CPMA (address 0016), bit 7 CPMA (address 0016), bit5 1 (Note) 1 (Note) RESET f(XCIN) (low-speed mode) selected as internal system clock Main clock f(XIN) oscillation stopped Note: Do not switch simultaneously. Return processing from power failure Set timer interrupt to occurs every second. Execute WIT instruction. At power failure, clock count is performed during timer interrupt processing (every second). When selecting main clock f(XIN) (high-speed mode) Detect power failure ? N Y Return condition from power failure completed ? N Y qX: This bit is not used here. Set it to “0” or “1” arbitrarily. |
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