MC68HC908AP16CFB datasheet(104/440 Pages) MOTOROLA

104 / 440 page

Clock Generator Module (CGM)

Data Sheet

MC68HC908AP Family — Rev. 2.5

104

MOTOROLA

Addr.

Bit 7

654321

Bit 0

$0036

PLL Control Register

(PTCL)

Read:

PLLIE

PLLF

PLLON

BCS

PRE1

PRE0

VPR1

VPR0

Write:

Reset:

00100000

$0037

PLL Bandwidth Control

(PBWC)

Read:

AUTO

LOCK

ACQ

0000

Write:

Reset:

0000000

$0038

PLL Multiplier Select

(PMSH)

Read:

0000

MUL11

MUL10

MUL9

MUL8

Write:

Reset:

00000000

$0039

PLL Multiplier Select

(PMSL)

Read:

MUL7

MUL6

MUL5

MUL4

MUL3

MUL2

MUL1

MUL0

Write:

Reset:

01000000

$003A

PLL VCO Range Select

(PMRS)

Read:

VRS7

VRS6

VRS5

VRS4

VRS3

VRS2

VRS1

VRS0

Write:

Reset:

01000000

$003B

PLL Reference Divider

Select Register

(PMDS)

Read:

0000

RDS3

RDS2

RDS1

RDS0

Write:

Reset:

0001

= Unimplemented

= Reserved

NOTES:

1. When AUTO = 0, PLLIE is forced clear and is read-only.

2. When AUTO = 0, PLLF and LOCK read as clear.

3. When AUTO = 1, ACQ is read-only.

4. When PLLON = 0 or VRS7:VRS0 = $0, BCS is forced clear and is read-only.

5. When PLLON = 1, the PLL programming register is read-only.

6. When BCS = 1, PLLON is forced set and is read-only.

Figure 8-2. CGM I/O Register Summary

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

MC68HC908AP16CFB Datasheet(PDF) 104 Page - Motorola, Inc

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