MC68HC908AP16CFB datasheet(107/440 Pages) MOTOROLA

107 / 440 page

Clock Generator Module (CGM)

Functional Description

MC68HC908AP Family — Rev. 2.5

Data Sheet

MOTOROLA

107

8.3.4 Acquisition and Tracking Modes

The PLL filter is manually or automatically configurable into one of two

operating modes:

•

Acquisition mode — In acquisition mode, the filter can make large

frequency corrections to the VCO. This mode is used at PLL start

up or when the PLL has suffered a severe noise hit and the VCO

frequency is far off the desired frequency. When in acquisition

mode, the ACQ bit is clear in the PLL bandwidth control register.

(See 8.5.2 PLL Bandwidth Control Register.)

•

Tracking mode — In tracking mode, the filter makes only small

corrections to the frequency of the VCO. PLL jitter is much lower

in tracking mode, but the response to noise is also slower. The

PLL enters tracking mode when the VCO frequency is nearly

correct, such as when the PLL is selected as the base clock

source. (See 8.3.8 Base Clock Selector Circuit.) The PLL is

automatically in tracking mode when not in acquisition mode or

when the ACQ bit is set.

8.3.5 Manual and Automatic PLL Bandwidth Modes

The PLL can change the bandwidth or operational mode of the loop filter

manually or automatically. Automatic mode is recommended for most

users.

In automatic bandwidth control mode (AUTO = 1), the lock detector

automatically switches between acquisition and tracking modes.

Automatic bandwidth control mode also is used to determine when the

VCO clock, CGMVCLK, is safe to use as the source for the base clock,

CGMOUT. (See 8.5.2 PLL Bandwidth Control Register.) If PLL

interrupts are enabled, the software can wait for a PLL interrupt request

and then check the LOCK bit. If interrupts are disabled, software can poll

the LOCK bit continuously (during PLL start-up, usually) or at periodic

intervals. In either case, when the LOCK bit is set, the VCO clock is safe

to use as the source for the base clock. (See 8.3.8 Base Clock Selector

Circuit.) If the VCO is selected as the source for the base clock and the

LOCK bit is clear, the PLL has suffered a severe noise hit and the

software must take appropriate action, depending on the application.

(See 8.6 Interrupts for information and precautions on using interrupts.)

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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