MC68HC908AP16CFB datasheet(148/440 Pages) MOTOROLA

148 / 440 page

System Integration Module (SIM)

Data Sheet

MC68HC908AP Family — Rev. 2.5

148

MOTOROLA

A break interrupt during stop mode sets the SIM break stop/wait bit

(SBSW) in the SIM break status register (SBSR).

The SIM counter is held in reset from the execution of the STOP

instruction until the beginning of stop recovery. It is then used to time the

recovery period. Figure 9-18 shows stop mode entry timing.

NOTE:

To minimize stop current, all pins configured as inputs should be driven

to a logic 1 or logic 0.

Figure 9-18. Stop Mode Entry Timing

Figure 9-19. Stop Mode Recovery from Interrupt or Break

9.7 SIM Registers

The SIM has three memory-mapped registers:

•

SIM Break Status Register (SBSR) — $FE00

•

SIM Reset Status Register (SRSR) — $FE01

•

SIM Break Flag Control Register (SBFCR) — $FE03

STOP ADDR + 1

SAME

IAB

IDB

PREVIOUS DATA

NEXT OPCODE

SAME

STOP ADDR

SAME

R/W

CPUSTOP

NOTE: Previous data can be operand data or the STOP opcode, depending on the last

instruction.

ICLK

INT/BREAK

IAB

STOP + 2

SP – 1

SP – 2

SP – 3

STOP +1

STOP RECOVERY PERIOD

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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