MC68HC908AP16CFB datasheet(149/440 Pages) MOTOROLA

149 / 440 page

System Integration Module (SIM)

SIM Registers

MC68HC908AP Family — Rev. 2.5

Data Sheet

MOTOROLA

149

9.7.1 SIM Break Status Register

The SIM break status register (SBSR) contains a flag to indicate that a

break caused an exit from stop mode or wait mode.

SBSW — Break Wait Bit

This status bit is set when a break interrupt causes an exit from wait

mode or stop mode. Clear SBSW by writing a logic 0 to it. Reset clears

SBSW.

1 = Stop mode or wait mode was exited by break interrupt

0 = Stop mode or wait mode was not exited by break interrupt

SBSW can be read within the break interrupt routine. The user can

modify the return address on the stack by subtracting 1 from it. The

following code is an example.

Address:

$FE00

Bit 7

654321

Bit 0

Read:

RRRRRR

SBSW

Write:

Note

Reset:

Note: Writing a logic 0 clears SBSW.

R= Reserved

Figure 9-20. SIM Break Status Register (SBSR)

This code works if the H register has been pushed onto the stack in the break

service routine software. This code should be executed at the end of the break

service routine software.

HIBYTE

EQU

LOBYTE

EQU

If not SBSW, do RTI

BRCLR

SBSW,SBSR, RETURN

;

See if wait mode or stop mode was exited by

break.

TST

LOBYTE,SP

;If RETURNLO is not zero,

BNE

DOLO

;then just decrement low byte.

DEC

HIBYTE,SP

;Else deal with high byte, too.

DOLO

DEC

LOBYTE,SP

;Point to WAIT/STOP opcode.

RETURN

PULH

RTI

;Restore H register.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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